Yi Ding

Method for achieving uniform chemical mechanical polishing in integrated circuit manufacturing

METHODS FOR FORMING FLOATING GATE MEMORY STRUCTURES

Method for providing STI structures with high coupling ratio in integrated circuit manufacturing

FLOATING GATE MEMORY STRUCTURES

Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges

Nonvolatile memory cell with multiple floating gates formed after the select gate

Nonvolatile memory cells with buried channel transistors

Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate

Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures

Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate

Fabrication of integrated circuit elements in structures with protruding features

Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer

Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit

Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit

Nonvolatile memories and methods of fabrication

Nonvolatile memories and methods of fabrication

Nonvolatile memory cells with buried channel transistors

Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures

Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures

Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures

Floating gate memory structures and fabrication methods

Nonvolatile memories and methods of fabrication

Nonvolatile memory cell with multiple floating gates formed after the select gate

Nonvolatile memory cell with multiple floating gates formed after the select gate

Nonvolatile memories with a floating gate having an upward protrusion

Integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges

Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates

Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions

Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask

Fabrication of conductive gates for nonvolatile memories from layers with protruding portions

Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates

Nonvolatile memory cell with multiple floating gates formed after the select gate

Fabrication of dielectric for a nonvolatile memory cell having multiple floating gates

Nonvolatile memory cells with buried channel transistors

Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions

Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates

Fabrication of gate dielectric in nonvolatile memories having select, floating and control gates

Fabrication of gate dielectric in nonvolatile memories having select, floating and control gates

Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions