Axel Preusse

Semiconductor structure including a layer of a first metal between a diffusion barrier layer and a second metal and method for the formation thereof

Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects

Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects

Contact elements of a semiconductor device formed by electroless plating and excess material removal with reduced sheer forces

Contact elements of a semiconductor device formed by electroless plating and excess material removal with reduced sheer forces

Contact elements of semiconductor devices formed on the basis of a partially applied activation layer

ENHANCED ELECTROMIGRATION PERFORMANCE OF COPPER LINES IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY SURFACE ALLOYING

Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices

Microstructure device including a metallization structure with self-aligned air gaps between closely spaced metal lines

Apparatus and method for removing bubbles from a process liquid

Reducing leakage in dielectric materials including metal regions including a metal cap layer in semiconductor devices

Metal cap layer of increased electrode potential for copper-based metal regions in semiconductor devices

METHOD OF FORMING A METAL DIRECTLY ON A CONDUCTIVE BARRIER LAYER BY ELECTROCHEMICAL DEPOSITION USING AN OXYGEN-DEPLETED AMBIENT

Method of forming a metal directly on a conductive barrier layer by electrochemical deposition using an oxygen-depleted ambient

METHOD OF FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING A CONDUCTIVE CAP LAYER BY AN ADVANCED INTEGRATION REGIME

METHOD OF FORMING A METAL LAYER OVER A PATTERNED DIELECTRIC BY ELECTROLESS DEPOSITION USING A SELECTIVELY PROVIDED ACTIVATION LAYER

Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime

SEMICONDUCTOR DEVICE COMPRISING A METALLIZATION LAYER STACK WITH A POROUS LOW-K MATERIAL HAVING AN ENHANCED INTEGRITY

Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase

Method of reducing wafer contamination by removing under-metal layers at the wafer edge

Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity

Technique for electrochemically depositing an alloy having a chemical order

Technique for metal deposition by electroless plating using an activation scheme including a substrate heating process

Method of reworking a semiconductor structure

Method and system for controlling a substrate position in an electrochemical process

Apparatus and method for removing bubbles from a process liquid

Method and system for controlling ion distribution during plating of a metal on a workpiece surface

System and method for an increased bath lifetime in a single-use plating regime

Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process

Method of forming a metal layer over patterned dielectric by electroless deposition using a catalyst

Method and system for automatically controlling a current distribution of a multi-anode arrangement during the plating of a metal on a substrate surface

Storage tank for process liquids with a reduced amount of bubbles

Apparatus and method for treating a substrate electrochemically while reducing metal corrosion