Inventor profile of:

Edward LAW

City:

Ladera Ranch, California

Country:

United States

Published Applications:

23

Last publication date:

2018-10-25

Top Assignees for applications by Edward LAW

The entities that hold a legal rights for patent applications filed by inventor LAW Edward:

Recent patent applications by LAW Edward

Edward LAW from Ladera Ranch, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-10-25
US20180308791A1
Electricity

Thin recon interposer package without TSV for fine input/output pitch fan-out

#2 | 2018-08-16
US20180233440A1
Electricity

RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE

#3 | 2017-01-12
US20170011993A1
Electricity

Thin recon interposer package without TSV for fine input/output pitch fan-out

#4 | 2016-10-13
US20160300661A1
Electricity

Embedded substrate core spiral inductor

#5 | 2016-02-18
US20160049348A1
Electricity

Semiconductor border protection sealant

#6 | 2015-11-26
US20150340308A1
Electricity

RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE

#7 | 2015-10-22
US20150303172A1
Electricity

RECONSTITUTION TECHNIQUES FOR SEMICONDUCTOR PACKAGES

#8 | 2015-10-22
US20150302974A1
Electricity

Magnetic-core three-dimensional (3D) inductors and packaging integration

#9 | 2014-03-27
US20140087553A1
Electricity

Fabricating a wafer level semiconductor package having a pre-formed dielectric layer

#10 | 2014-03-27
US20140084462A1
Electricity

Wafer level semiconductor package

#11 | 2013-05-30
US20130134596A1
Electricity

Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layer

#12 | 2013-03-28
US20130075917A1
Electricity

Multi-chip and multi-substrate reconstitution based packaging

#13 | 2013-01-03
US20130001791A1
Electricity

Method and apparatuses for integrated circuit substrate manufacture

#14 | 2012-11-29
US20120299187A1
Electricity

Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products

#15 | 2012-09-27
US20120241955A1
Electricity

Chip scale package assembly in reconstitution panel process format

#16 | 2012-09-27
US20120241951A1
Electricity

WAFER BUMPING USING PRINTED UNDER BUMP METALIZATION

#17 | 2012-07-26
US20120187545A1
Electricity

DIRECT THROUGH VIA WAFER LEVEL FANOUT PACKAGE

#18 | 2012-07-12
US20120175773A1
Electricity

Thermal enhanced package using embedded substrate

#19 | 2011-05-19
US20110115075A1
Electricity

Bumping free flip chip process

#20 | 2011-05-19
US20110115074A1
Electricity

WAFER BUMPING USING PRINTED UNDER BUMP METALIZATION

#21 | 2009-08-06
US20090194872A1
Electricity

DEPOPULATING INTEGRATED CIRCUIT PACKAGE BALL LOCATIONS TO ENABLE IMPROVED EDGE CLEARANCE IN SHIPPING TRAY

#22 | 2008-04-24
US20080096312A1
Electricity

Low profile ball grid array (BGA) package with exposed die and method of making same

#23 | 2007-11-29
US20070273023A1
Electricity

Integrated circuit package having exposed thermally conducting body

InventorID:

4368 ⎘