Eric A. Foreman

Partial parameters and projection thereof included within statistical timing analysis

Independently projecting a canonical clock

Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit

Multi-sided variations for creating integrated circuits

Multi-sided variations for creating integrated circuits

Multi-sided variations for creating integrated circuits

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Voltage and frequency balancing at nominal point

Voltage and frequency balancing at nominal point

Voltage and frequency balancing at nominal point

Voltage and frequency balancing at nominal point

Integrating manufacturing feedback into integrated circuit structure design

Addressing of process and voltage points

Timing optimization driven by statistical sensitivites

Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit

Adaptive characterization and instantiation of timing abstracts

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Controlling right-of-way for priority vehicles

Emergency responsive navigation

Integrated circuit chip design methods and systems using process window-aware timing analysis

Scaling voltages in relation to die location

Method and system for timing violations in a circuit

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

Variable accuracy parameter modeling in statistical timing

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Dynamic voltage frequency scaling

Variable accuracy parameter modeling in statistical timing

Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling

Collapsing terms in statistical static timing analysis

Scaling voltages in relation to die location

INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION

System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time

Partial parameters and projection thereof included within statistical timing analysis

Balancing sensitivities with respect to timing closure for integrated circuits

Modeling multi-patterning variability with statistical timing

DETERMINING PROCESS VARIATION USING DEVICE THRESHOLD SENSITIVITES

Controlling circuit voltage and frequency based upon location-dependent temperature

Hierarchical design of integrated circuits with multi-patterning requirements

Reducing runtime and memory requirements of static timing analysis

Selective voltage binning within a three-dimensional integrated chip stack

Power/performance optimization through continuously variable temperature-based voltage control

Parasitic extraction in an integrated circuit with multi-patterning requirements

Frequency selection with selective voltage binning

Modeling multi-patterning variability with statistical timing

Hierarchical design of integrated circuits with multi-patterning requirements

Modeling multi-patterning variability with statistical timing

Parasitic extraction in an integrated circuit with multi-patterning requirements

Systems and methods for correlated parameters in statistical static timing analysis

Adaptive power control using timing canonicals

Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures

Power/performance optimization through temperature/voltage control

Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures

Systems and methods for correlated parameters in statistical static timing analysis

Statistical clock cycle computation

Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

Statistical single library including on chip variation for rapid timing and power analysis

Efficient slack projection for truncated distributions

Systems and methods for correlated parameters in statistical static timing analysis

Integrating manufacturing feedback into integrated circuit structure design

System and method for efficient modeling of NPskew effects on static timing tests

Method for modeling variation in a feedback loop of a phase-locked loop

Method to reduce delay variation by sensitivity cancellation

Chip design and fabrication method optimized for profit

Method of performing timing analysis on integrated circuit chips with consideration of process variations

Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing

Methods for identifying failing timing requirements in a digital design

Methods for practical worst test definition and debug during block based statistical static timing analysis

Method to quickly estimate inductance for timing models

Method to identify timing violations outside of manufacturing specification limits

TIMING CLOSURE USING MULTIPLE TIMING RUNS WHICH DISTRIBUTE THE FREQUENCY OF IDENTIFIED FAILS PER TIMING CORNER

Method and system for evaluating timing in an integrated circuit

IC chip at-functional-speed testing with process coverage evaluation

Slack sensitivity to parameter variation based timing analysis

Variable threshold system and method for multi-corner static timing analysis

Parameter ordering for multi-corner static timing analysis

Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis

Estimation of process variation impact of slack in multi-corner path-based static timing analysis

Slack sensitivity to parameter variation based timing analysis

Prioritizing of nets for coupled noise analysis

Method and system for evaluating timing in an integrated circuit

Slack sensitivity to parameter variation based timing analysis

Method and system for evaluating timing in an integrated circuit