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Inventor profile of:

Chia-Lin Chen

City:

Hsinchu

Country:

Taiwan

Published Applications:

19

Last publication date:

2025-10-02

Top Assignees for applications by Chia-Lin Chen

The entities that hold a legal rights for patent applications filed by inventor Chen Chia-Lin:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 7 Hsin-Chu, Taiwan
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 4 Hsin-Chu, Taiwan
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION 2 HSINCHU, Taiwan
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 2 Hsinchu, Taiwan
Powerchip Semiconductor Manufacturing Corporation 1 Hsinchu, Taiwan

Recent patent applications by Chen Chia-Lin

Chia-Lin Chen from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-10-02

US20250311464A1

CMOS IMAGE SENSOR WITH TRENCH CAPACITOR AND METHOD OF MANUFACTURING THE SAME

#2 | 2022-05-12

US20220148938A1

Semiconductor structure

#3 | 2020-11-05

US20200348355A1

Reliability determination method

#4 | 2007-10-18

US20070240826A1

Gas supply device and apparatus for gas etching or cleaning substrates

#5 | 2007-05-10

US20070105337A1

Selective nitride liner formation for shallow trench isolation

#6 | 2006-11-21

US10831874

Method of generating multiple oxides by plasma nitridation on oxide

#7 | 2006-10-10

US10831871

Method of generating multiple oxides by plasma nitridation on oxide

#8 | 2006-08-17

US20060183279A1

METHOD FOR SELECTIVELY STRESSING MOSFETS TO IMPROVE CHARGE CARRIER MOBILITY

#9 | 2006-05-11

US20060099771A1

Selective nitride liner formation for shallow trench isolation

#10 | 2006-03-09

US20060049470A1

Double layer polysilicon gate electrode

#11 | 2006-01-19

US20060014396A1

Method for forming high selectivity protection layer on semiconductor device

#12 | 2005-09-29

US20050214998A1

Local stress control for CMOS performance enhancement

#13 | 2005-09-15

US20050199958A1

Method for selectively stressing MOSFETs to improve charge carrier mobility

#14 | 2005-08-25

US20050186750A1

Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process

#15 | 2005-07-21

US20050159008A1

High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer

#16 | 2005-06-23

US20050136583A1

Advanced strained-channel technique to improve CMOS performance

#17 | 2005-06-09

US20050121671A1

Laminated silicon gate electrode

#18 | 2005-03-17

US20050056900A1

Method and structure for forming high-k gates

#19 | 2005-03-01

US10274570

Method for fabricating laminated silicon gate electrode

InventorID:

4409205 ⎘