Brian T. Vanderpool

Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar

Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar

Oldest link first arbitration between links grouped as single arbitration elements

Oldest link first arbitration between links grouped as single arbitration elements

Peripheral component interconnect express (PCIe) ping in a switch-based environment

Peripheral component interconnect express (PCIe) ping in a switch-based environment

Selective underflow protection in a network switch

Selective underflow protection in a network switch

Computer-based flow synchronization for efficient multicast forwarding for products and services

Multicast packet routing via crossbar bypass paths

Multicast packet routing via crossbar bypass paths

Facilitating resource use in multicyle arbitration for single cycle data transfer

Facilitating resource use in multicycle arbitration for single cycle data transfer

Queue credit management

Implementing hierarchical high radix switch with timesliced crossbar

Queue credit management

Integrated link-based data recorder for semiconductor chip

Integrated link-based data recorder for semiconductor chip

Input buffered switching device including bypass logic

Weightage-based scheduling for hierarchical switching fabrics

Multicast bandwidth multiplication for a unified distributed switch

Multicast bandwidth multiplication for a unified distributed switch

Reducing Memory Fetch Latency Using Next Fetch Hint

Early header CRC in data response packets with variable gap count

Early header CRC in data response packets with variable gap count

Early header CRC in data response packets with variable gap count

Fairness, Performance, and Livelock Assessment Using a Loop Manager With Comparative Parallel Looping

Method for tuning chipset parameters to achieve optimal performance under varying workload types

Memory controller granular read queue dynamic optimization of command selection

Memory Controller Read Queue Dynamic Optimization of Command Selection

Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory

Method, Apparatus, and System Supporting Improved DMA Writes

Method, Apparatus, System and Program Product Supporting Efficient Eviction of an Entry From a Central Coherence Directory

Method, Apparatus, System and Program Product Supporting Directory-Assisted Speculative Snoop Probe With Concurrent Memory Access

Structure for silent invalid state transition handling in an SMP environment

Prioritization of out-of-order data transfers on shared data bus

Silent invalid state transition handling in an SMP environment

Patrol snooping for higher level cache eviction candidate identification

Early return indication for return data prior to receiving all responses in shared memory architecture

Eviction algorithm for inclusive lower level cache based upon state of higher level cache

Early return indication for read exclusive requests in shared memory architecture

Selecting a command to send to memory

Derivative performance counter mechanism

Early coherency indication for return data in shared memory architecture

Methods and apparatus for processing a command

Prioritization of out-of-order data transfers on shared data bus