Mauricio J. Serrano

Scalable Switch Capacitor Computation Cores for Accurate and Efficient Deep Learning Inference

Dual phase matrix-vector multiplication system

SMT processor to create a virtual vector register file for a borrower thread from a number of donated vector register files

Dual phase matrix-vector multiplication system

Instruction prefetching in a computer processor using a prefetch prediction vector

Wide vector execution in single thread mode for an out-of-order processor

Wide vector execution in single thread mode for an out-of-order processor

Dynamic sequential instruction prefetching

Switching matrix representation for an incremental algorithm computing connected components

Reducing memory access latency in scatter/gather operations

Techniques for dynamic sequential instruction prefetching

Instruction prefetching in a computer processor using a prefetch prediction vector

Branch prediction using multiple versions of history data

Branch prediction using multiple versions of history data

Branch prediction using multiple versions of history data

Redundant transactions for detection of timing sensitive errors

Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes

Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes

Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

Predicting indirect branches using problem branch filtering and pattern cache

Branch prediction using multiple versions of history data

Compressed indirect prediction caches

Detection of hardware errors using redundant transactions for system test

Redundant transactions for detection of timing sensitive errors

Tracking long GHV in high performance out-of-order superscalar processors

Transactions for checkpointing and reverse execution

Hardware-assisted program trace collection with selectable call-signature capture

HARDWARE-ASSISTED PROGRAM TRACE COLLECTION WITH SELECTABLE CALL-SIGNATURE CAPTURE

Tracking a programs calling context using a hybrid code signature

Redundant Transactional Memory

Reducing Overhead and Increasing Precision with Code Instrumentation

Adaptive next-executing-cycle trace selection for trace-driven code optimizers

Branch trace history compression

Data placement optimization using data context collected during garbage collection

Mechanism for data cache replacement based on region policies

Preferred write-mostly data cache replacement policies

Target branch prediction using a plurality of tables

System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries