Andrew C. Russell

Soft error detection in a memory system

Soft error detection in a memory system

Content addressable memory with error detection

Edge coupling of semiconductor dies

System with feature of saving dynamic power of flip-flop banks

Method and apparatus for reducing the number of speculative accesses to a memory array

Memory with power savings for unnecessary reads

Memory using voltage to improve reliability for certain data types

Memory having improved reliability for certain data types

Data type dependent memory scrubbing

Selective memory scrubbing based on data type

Memory with word line access control

Multi-port register file with multiplexed data

Memory column drowsy control

System and method for cache access

Write contention-free, noise-tolerant multi-port bitcell

Methods for testing a memory embedded in an integrated circuit

Memory voltage regulator with leakage current voltage control

Electronic circuit having shared leakage current reduction circuits

Memory with low voltage mode operation

Data processing having multiple low power modes and method therefor

Multi-port memory having a variable number of used write ports

Integrated circuit having variable memory array power supply voltage

Memory using multiple supply voltages

SRAM with read and write assist

Memory with read cycle write back

INTEGRATED CIRCUIT HAVING LOW POWER MODE VOLTAGE REGULATOR

Integrated circuit having memory repair information storage and method therefor

Integrated circuit memory having assisted access and method therefor

Integrated circuit having an embedded memory and method for testing the memory

Voltage-based memory size scaling in a data processing system

Level shifter for change of both high and low voltage

Integrated circuit having memory with configurable read/write operations and method therefor

Shared resource based thread scheduling with affinity and/or selectable criteria

Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array

Byte writeable memory with bit-column voltage selection and column redundancy

Memory with increased write margin bitcells

Controlled reliability in an integrated circuit

Dynamic scannable latch and method of operation

Minimum memory operating voltage technique

Integrated circuit having a memory with low voltage read/write operation

Integrated circuit having a memory with low voltage read/write operation

Memory circuit