Parker, Texas
United States
769
2025-12-18
The entities that hold a legal rights for patent applications filed by inventor Whetsel Lee D.:
Lee D. Whetsel from Parker, US has applied for patents for these inventions. The list has both pending applications and granted patents:
FALLING CLOCK EDGE JTAG BUS ROUTERS
#2 | 2025-11-13TEST CIRCUIT IN DIE STACK
#3 | 2025-09-18INTERPOSER CIRCUIT
#4 | 2025-08-21INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
#5 | 2025-05-15DEVICE ACCESS PORT SELECTION
#6 | 2025-04-24AT-SPEED TEST ACCESS PORT OPERATIONS
#7 | 2025-03-273D TAP & SCAN PORT ARCHITECTURES
#8 | 2025-03-20THROUGH-SILICON VIA (TSV) TESTING
#9 | 2025-03-13SCAN TESTABLE THROUGH SILICON VIAS
#10 | 2025-03-13COMMANDED JTAG TEST ACCESS PORT OPERATIONS
#11 | 2025-02-13INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
#12 | 2024-12-05SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
#13 | 2024-11-21ADDRESSABLE TEST ACCESS PORT
#14 | 2024-10-17Integrated circuit die test architecture
#15 | 2024-10-10PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER
#16 | 2024-09-263D STACKED DIE TEST ARCHITECTURE
#17 | 2024-08-08TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT
#18 | 2024-06-06MULTIPLE ACCESS PORT CIRCUITS
#19 | 2024-04-25INTERPOSER INSTRUMENTATION METHOD AND APPARATUS
#20 | 2024-03-21INTERPOSER CIRCUIT
#21 | 2024-03-21TSV testing
#22 | 2024-02-22At-speed test access port operations
#23 | 2024-01-18Selectable JTAG or trace access with data store and output
#24 | 2024-01-11Scan testing using scan frames with embedded commands
#25 | 2023-12-283D tap and scan port architectures
#26 | 2023-12-14Addressable test access port
#27 | 2023-11-30SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
#28 | 2023-11-16Integrated circuit die test architecture
#29 | 2023-10-19FALLING CLOCK EDGE JTAG BUS ROUTERS
#30 | 2023-10-19Test access port with address and command capability
#31 | 2023-10-123D stacked die test architecture
#32 | 2023-09-21Device access port selection
#33 | 2023-08-31Array of Through-Silicon Via Contact Points on a Semiconductor Die
#34 | 2023-08-31TESTING INTERPOSER METHOD AND APPARATUS
#35 | 2023-08-24Test compression in a JTAG daisy-chain environment
#36 | 2023-08-17Scan frame based test access mechanisms
#37 | 2023-08-10Interface to full and reduced pin JTAG devices
#38 | 2023-07-20Device testing architecture, method, and system
#39 | 2023-07-13Commanded JTAG test access port operations
#40 | 2023-06-29Interposer circuit
#41 | 2023-06-22AT-speed test access port operations
#42 | 2023-06-22Shadow access port method and apparatus
#43 | 2023-06-08Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO
#44 | 2023-05-25Wafer scale testing using a 2 signal JTAG interface
#45 | 2023-05-253D TAP and scan port architectures
#46 | 2023-02-23Reduced signaling interface method and apparatus
#47 | 2022-12-29Apparatus for device access port selection
#48 | 2022-12-013D stacked die test architecture
#49 | 2022-10-27Integrated circuit die test architecture
#50 | 2022-10-06TSV testing using test circuits and grounding means
#51 | 2022-08-18Interposer instrumentation method and apparatus
#52 | 2022-07-21Scan testable through silicon VIAs
#53 | 2022-06-23At-speed test access port operations
#54 | 2022-05-26Scan frame based test access mechanisms
#55 | 2022-05-12Selectable JTAG or trace access with data store and output
#56 | 2022-05-12Commanded JTAG test access port operations
#57 | 2022-05-05Direct scan access JTAG
#58 | 2022-04-14Wafer scale testing using a 2 signal JTAG interface
#59 | 2022-04-14TSV testing method and apparatus
#60 | 2022-04-073D tap and scan port architectures
#61 | 2022-03-10Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO
#62 | 2022-03-03Test access port with address and command capability
#63 | 2022-02-10Addressable test access port apparatus
#64 | 2022-01-20IEEE 1149.1 interposer apparatus
#65 | 2021-12-30Scan testing using scan frames with embedded commands
#66 | 2021-12-23Shadow access port integrated circuit
#67 | 2021-12-09Device testing architecture of an integrated circuit
#68 | 2021-11-25Two pin serial bus communication interface and process
#69 | 2021-11-18Test compression in a JTAG daisy-chain environment
#70 | 2021-10-28Interface to full and reduced pin JTAG devices
#71 | 2021-10-21Integrated circuit with reduced signaling interface
#72 | 2021-09-023D stacked die test architecture
#73 | 2021-07-15JTAG bus communication method and apparatus
#74 | 2021-06-10Interposer instrumentation method and apparatus
#75 | 2021-06-03Apparatus for device access port selection
#76 | 2021-05-20Falling clock edge JTAG bus routers
#77 | 2021-05-20Integrated circuit die test architecture
#78 | 2021-05-06Testing interposer method and apparatus
#79 | 2021-04-08TSV testing using test circuits and grounding means
#80 | 2021-03-253D tap and scan port architectures
#81 | 2021-03-25Tap, command, router circuitry, and data register
#82 | 2021-03-25Wafer scale testing using a 2 signal JTAG interface
#83 | 2021-03-11Reduced signaling interface circuit
#84 | 2021-02-11Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO
#85 | 2021-02-11Test access port with address and command capability
#86 | 2021-02-04Test access port with address and command capability
#87 | 2020-12-31Scan testable through silicon VIAs
#88 | 2020-12-31TSV testing method and apparatus
#89 | 2020-12-10Selectable JTAG or trace access with data store and output
#90 | 2020-10-08IC analog boundary scan cell, digital cell, comparator, analog switches
#91 | 2020-09-03Direct scan access JTAG
#92 | 2020-09-03Scan frame based test access mechanisms
#93 | 2020-09-03Integrated circuit with JTAG port, tap linking module, and off-chip TAP interface port
#94 | 2020-09-03Die testing using top surface test pads
#95 | 2020-08-20Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO
#96 | 2020-07-09Test compression in a JTAG daisy-chain environment
#97 | 2020-07-09TAP,TCK inverter,shadow access port scan/instruction registers,state machine
#98 | 2020-07-09Commanded JTAG test access port operations
#99 | 2020-06-18TSVS, test circuits, scan cells, comparators, electrical source, and resistor
#100 | 2020-06-18Stacked die interposer monitor trigger, address comparator, trigger controller circuitry
45079 ⎘