Ossining, New York
United States
42
2020-05-07
The entities that hold a legal rights for patent applications filed by inventor Khan Babar A.:
Babar A. Khan from Ossining, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices
#2 | 2020-02-13Semiconductor structures with deep trench capacitor and methods of manufacture
#3 | 2019-09-12Semiconductor structures with deep trench capacitor and methods of manufacture
#4 | 2019-07-04Semiconductor structures with deep trench capacitor and methods of manufacture
#5 | 2018-11-22Semiconductor structures with deep trench capacitor and methods of manufacture
#6 | 2018-10-04Semiconductor structures with deep trench capacitor and methods of manufacture
#7 | 2018-08-09Semiconductor structures with deep trench capacitor and methods of manufacture
#8 | 2017-07-27Semiconductor structures with deep trench capacitor and methods of manufacture
#9 | 2017-06-22Cooling and power delivery for a wafer level computing board
#10 | 2017-04-27Semiconductor structures with deep trench capacitor and methods of manufacture
#11 | 2017-01-26Semiconductor structures with deep trench capacitor and methods of manufacture
#12 | 2016-12-15Vertically integrated memory cell
#13 | 2016-06-23Semiconductor structures with deep trench capacitor and methods of manufacture
#14 | 2016-06-23SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE
#15 | 2016-06-09Wet bottling process for small diameter deep trench capacitors
#16 | 2016-04-07Method of forming integrated fin and strap structure for an access transistor of a trench capacitor
#17 | 2016-01-28Dummy gate structure for electrical isolation of a fin DRAM
#18 | 2015-12-03Vertically integrated memory cell
#19 | 2015-07-23Dummy gate structure for electrical isolation of a fin DRAM
#20 | 2015-05-14Semiconductor structures including an integrated FinFET with deep trench capacitor and methods of manufacture
#21 | 2015-02-05FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM
#22 | 2015-01-22Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)
#23 | 2015-01-22Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture
#24 | 2014-10-09Integrated fin and strap structure for an access transistor of a trench capacitor
#25 | 2014-09-18Semiconductor structures with deep trench capacitor and methods of manufacture
#26 | 2014-07-10Semiconductor-on-oxide structure and method of forming
#27 | 2014-06-05Uniform finFET gate height
#28 | 2014-03-27Semiconductor-on-insulator (SOI) deep trench capacitor
#29 | 2014-03-06DRAM with dual level word lines
#30 | 2014-02-06Structure and method to realize conformal doping in deep trench applications
#31 | 2014-02-06Structure And Method To Realize Conformal Doping In Deep Trench Applications
#32 | 2014-01-23Creating deep trenches on underlying substrate
#33 | 2014-01-23DRAM with dual level word lines
#34 | 2013-12-05FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM
#35 | 2013-10-31Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)
#36 | 2013-10-03Semiconductor-on-oxide structure and method of forming
#37 | 2013-09-26Creating deep trenches on underlying substrate
#38 | 2012-09-13Technique to create a buried plate in embedded dynamic random access memory device
#39 | 2012-04-12Technique to create a buried plate in embedded dynamic random access memory device
#40 | 2010-02-18Structure and method for manufacturing trench capacitance
#41 | 2006-07-27Trench capacitor array having well contacting merged plate
#42 | 2006-06-08Collarless trench DRAM device
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