Edward Preisler

Method and Structure for High Precision Silicon Nitride Photonics Devices

Method for Fabricating a High Voltage Breakdown Resistant Bipolar Transistor

Low Resistivity Ohmic Contact to Group III-V Device

Thin Film Pockels Material-Based Photonics Structure Incorporating an Optoelectronic Device

Method for Forming a Tantalum Nitride Resistive Heater for Thermally-Tunable Photonics Devices

Method for Integration of Tantalum Nitride Resistive Heater for Photonics Devices and Related Structure

High Voltage Breakdown Resistant Bipolar Transistor

Method for Integration of Optoelectronic Devices Comprising Pockels Materials

Integration of optoelectronic devices comprising lithium niobate or other Pockels materials

Platinum-Based Solder Body Contacts for Integration of a First Substrate with a Second Substrate

Efficient Integration of a First Substrate without Solder Bumps with a Second Substrate Having Solder Bumps

Tantalum Nitride Resistive Heater for Thermally-Tunable Photonics Devices

Stress-Reduced Silicon Photonics Semiconductor Wafer

Method for manufacturing a semiconductor structure having group III-V device on group IV substrate and contacts with liner stacks

Method of manufacturing bipolar complementary-metal-oxide-semiconductor (BiCMOS) devices using nickel silicide

Nickel Silicide in Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) Device

Method of manufacturing nickel silicide in bipolar complementary-metal-oxide-semiconductor (BiCMOS)

Nickel silicide in bipolar complementary-metal-oxide-semiconductor (BiCMOS) device and method of manufacturing

Method for Forming a Semiconductor Structure Having a Porous Semiconductor Layer in RF Devices

Semiconductor structure having group III-V chiplet on group IV substrate and cavity in proximity to heating element

Semiconductor structure having group III-V device on group IV substrate

Group III-V device on group IV substrate using contacts with precursor stacks

Semiconductor structure having group III-V device on group IV substrate and contacts with precursor stacks

Structure and method for process control monitoring for group III-V devices integrated with group IV substrate

Fabrication of semiconductor structure having group III-V device on group IV substrate with separately formed contacts using different metal liners

Semiconductor structure having group III-V device on group IV substrate and contacts with liner stacks

Semiconductor structure having porous semiconductor segment for RF devices and bulk semiconductor region for non-RF devices

Semiconductor structure having porous semiconductor layer for RF devices

Integrated optical/electrical probe card for testing optical, electrical, and optoelectronic devices in a semiconductor die

Germanium on insulator for CMOS imagers in the short wave infrared

Method for fabrication of germanium photodiode with silicon cap

Anode up—cathode down silicon and germanium photodiode

Germanium photodiode with silicon cap

Silicon-on-insulator (SOI) die including a light emitting layer pedestal-aligned with a light receiving segment

Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology

BiCMOS integration with reduced masking steps

BiCMOS integration using a shared SiGe layer

Efficient fabrication of BiCMOS devices

Low-cost complementary BiCMOS integration scheme

Heterojunction bipolar transistor having a germanium extrinsic base utilizing a sacrificial emitter post

Heterojunction bipolar transistor having a germanium raised extrinsic base

Isolated through silicon vias in RF technologies

Isolated through silicon via and isolated deep silicon via having total or partial isolation

Semiconductor fabrication utilizing grating and trim masks

Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure