PHILLIP G. WILLIAMS

Adaptively enabling and disabling snooping bus commands

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING INSTRUCTION FUSION

Adaptively enabling and disabling snooping bus commands

Operation of a multi-slice processor implementing datapath steering

Operation of a multi-slice processor implementing datapath steering

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor using null internal operations (IOPs)

Thread migration using a microcode engine of a multi-slice processor

Hybrid replacement policy in a multilevel cache memory hierarchy

Cache backing store for transactional memory

Cache backing store for transactional memory

Techniques for preserving an invalid global domain indication when installing a shared cache line in a cache

Preserving an invalid global domain indication when installing a shared cache line in a cache

Adaptively enabling and disabling snooping fastpath commands

Adaptively enabling and disabling snooping fastpath commands

Virtual machine failover

Virtual machines failover

Data cache block deallocate requests in a multi-level cache hierarchy

Data cache block deallocate requests

Data cache block deallocate requests in a multi-level cache hierarchy

Data cache block deallocate requests

Formation of an exclusive ownership coherence state in a lower level cache upon replacement from an upper level cache of a cache line in a private shared owner state

Delete of cache line with correctable error

Updating partial cache lines in a data processing system

Mode-based castout destination selection

Lateral castout target selection

Empirically based dynamic control of transmission of victim cache lateral castouts

Lateral castout (LCO) of victim cache line in data-invalid state

Handling castout cache lines in a victim cache

Lateral cache-to-cache cast-in

Victim cache prefetching

Providing pseudo-randomized static values during LBIST transition tests

Victim cache replacement

Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing

Processor, data processing system and method supporting a shared global coherency state

System and method of responding to a cache read error with a temporary cache directory column delete

Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory

Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory