S. Brandon Keller

System and method for determining detail of analysis in a circuit design

System and method for processing configuration information

System and method for controlling activity of temporary files in a computer system

System and method to optimize logical configuration relationships in VLSI circuit analysis tools

System and method to limit runtime of VLSI circuit analysis tools for complex electronic circuits

System and method for flattening hierarchical designs in VLSI circuit analysis tools

System and method for facilitating efficient application of logical configuration information in VLSI circuit analysis tools

System and method to prioritize and selectively apply configuration information for VLSI circuit analysis tools

System and method for controlling analysis of multiple instantiations of circuits in hierarchical VLSI circuit designs

System and method for determining connectivity of nets in a hierarchical circuit design

Systems and methods for establishing data model consistency of computer aided design tools

System and method for determining unmatched design elements in a computer-automated design

Systems and methods for performing circuit analysis on a circuit design

System and method for determining wire capacitance for a VLSI circuit

System and method for determining a highest level signal name in a hierarchical VLSI design

System and method for iteratively traversing a hierarchical circuit design

Systems and methods utilizing fast analysis information during detailed analysis of a circuit design

Systems and methods for identifying data sources associated with a circuit design

Computer aided design systems and methods with reduced memory utilization

System and method analyzing design elements in computer aided design tools

System and method for determining applicable configuration information for use in analysis of a computer aided design

Systems and methods for determining activity factors of a circuit design