Inventor profile of:

Johnathan E. Faltermeier

City:

Delanson, New York

Country:

United States

Published Applications:

31

Last publication date:

2018-03-22

Top Assignees for applications by Johnathan E. Faltermeier

The entities that hold a legal rights for patent applications filed by inventor Faltermeier Johnathan E.:

Recent patent applications by Faltermeier Johnathan E.

Johnathan E. Faltermeier from Delanson, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-03-22
US20180083117A1
Electricity

Replacement metal gate stack for diffusion prevention

#2 | 2017-05-18
US20170140994A1
Electricity

Gate structure cut after formation of epitaxial active regions

#3 | 2016-07-07
US20160197157A1
Electricity

Replacement metal gate stack for diffusion prevention

#4 | 2016-02-04
US20160035616A1
Electricity

Handler wafer removal by use of sacrificial inert layer

#5 | 2016-01-28
US20160027700A1
Electricity

Gate structure cut after formation of epitaxial active regions

#6 | 2016-01-19
US14465365
Electricity

finFETs containing improved strain benefit and self aligned trench isolation structures

#7 | 2015-12-17
US20150364476A1
Electricity

Semiconductor structure having buried conductive elements

#8 | 2015-09-10
US20150255458A1
Electricity

Replacement metal gate stack for diffusion prevention

#9 | 2015-08-20
US20150236024A1
Electricity

Semiconductor structure having buried conductive elements

#10 | 2015-07-30
US20150214219A1
Electricity

Gate structure cut after formation of epitaxial active regions

#11 | 2014-06-05
US20140151772A1
Electricity

Uniform finFET gate height

#12 | 2014-05-15
US20140131801A1
Electricity

FinFET spacer formation by oriented implantation

#13 | 2013-08-08
US20130203234A1
Electricity

Highly scalable trench capacitor

#14 | 2013-01-24
US20130020642A1
Electricity

FinFET spacer formation by oriented implantation

#15 | 2012-12-06
US20120305940A1
Electricity

Defect Free Si:C Epitaxial Growth

#16 | 2012-11-08
US20120280250A1
Electricity

Spacer as hard mask scheme for in-situ doping in CMOS finFETs

#17 | 2012-07-05
US20120168775A1
Electricity

Stress enhanced transistor devices and methods of making

#18 | 2011-08-25
US20110204384A1
Electricity

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

#19 | 2011-05-05
US20110101455A1
Electricity

FinFET spacer formation by oriented implantation

#20 | 2011-02-10
US20110031503A1
Electricity

DEVICE WITH STRESSED CHANNEL

#21 | 2010-11-25
US20100295127A1
Electricity

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

#22 | 2010-08-19
US20100210098A1
Electricity

Self-aligned contact

#23 | 2010-07-29
US20100187578A1
Electricity

Stress enhanced transistor devices and methods of making

#24 | 2010-02-25
US20100048027A1
Electricity

Smooth and vertical semiconductor fin structure

#25 | 2009-10-29
US20090267149A1
Electricity

Source/drain junction for high performance MOSFET formed by selective EPI process

#26 | 2009-07-09
US20090174031A1
Electricity

DRAM having deep trench capacitors with lightly doped buried plates

#27 | 2009-07-09
US20090173980A1
Electricity

Providing isolation for wordline passing over deep trench capacitor

#28 | 2009-07-02
US20090170331A1
Electricity

METHOD OF FORMING A BOTTLE-SHAPED TRENCH BY ION IMPLANTATION

#29 | 2009-04-23
US20090104776A1
Electricity

METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES

#30 | 2009-02-19
US20090047791A1
Electricity

SEMICONDUCTOR ETCHING METHODS

#31 | 2008-03-27
US20080076230A1
Electricity

Trench capacitor with void-free conductor fill

InventorID:

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