Delanson, New York
United States
31
2018-03-22
The entities that hold a legal rights for patent applications filed by inventor Faltermeier Johnathan E.:
Johnathan E. Faltermeier from Delanson, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Replacement metal gate stack for diffusion prevention
#2 | 2017-05-18Gate structure cut after formation of epitaxial active regions
#3 | 2016-07-07Replacement metal gate stack for diffusion prevention
#4 | 2016-02-04Handler wafer removal by use of sacrificial inert layer
#5 | 2016-01-28Gate structure cut after formation of epitaxial active regions
#6 | 2016-01-19finFETs containing improved strain benefit and self aligned trench isolation structures
#7 | 2015-12-17Semiconductor structure having buried conductive elements
#8 | 2015-09-10Replacement metal gate stack for diffusion prevention
#9 | 2015-08-20Semiconductor structure having buried conductive elements
#10 | 2015-07-30Gate structure cut after formation of epitaxial active regions
#11 | 2014-06-05Uniform finFET gate height
#12 | 2014-05-15FinFET spacer formation by oriented implantation
#13 | 2013-08-08Highly scalable trench capacitor
#14 | 2013-01-24FinFET spacer formation by oriented implantation
#15 | 2012-12-06Defect Free Si:C Epitaxial Growth
#16 | 2012-11-08Spacer as hard mask scheme for in-situ doping in CMOS finFETs
#17 | 2012-07-05Stress enhanced transistor devices and methods of making
#18 | 2011-08-25Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
#19 | 2011-05-05FinFET spacer formation by oriented implantation
#20 | 2011-02-10DEVICE WITH STRESSED CHANNEL
#21 | 2010-11-25Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
#22 | 2010-08-19Self-aligned contact
#23 | 2010-07-29Stress enhanced transistor devices and methods of making
#24 | 2010-02-25Smooth and vertical semiconductor fin structure
#25 | 2009-10-29Source/drain junction for high performance MOSFET formed by selective EPI process
#26 | 2009-07-09DRAM having deep trench capacitors with lightly doped buried plates
#27 | 2009-07-09Providing isolation for wordline passing over deep trench capacitor
#28 | 2009-07-02METHOD OF FORMING A BOTTLE-SHAPED TRENCH BY ION IMPLANTATION
#29 | 2009-04-23METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES
#30 | 2009-02-19SEMICONDUCTOR ETCHING METHODS
#31 | 2008-03-27Trench capacitor with void-free conductor fill
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