Robert John Allen

BLOCKAGE AWARE FLUE ROUTING IN BUFFER BAYS

PARALLEL CREATION OF VIA MESHES IN AN INTEGRATED CIRCUIT

DATA-DRIVEN CUTOUT FOR MIXED TRANSISTOR-LEVEL AND ABSTRACT-BASED TIMING ANALYSIS

TIMING-AWARE FILL

RETARGETING-AWARE FILL

TRANSLATION OF INTEGRATED CIRCUIT DESIGN DATA INTO A PRODUCTION FORMAT

TIMING CONSTRAINT AUTO-CREATION FOR INTEGRATED CIRCUIT TESTING

DENSITY-AWARE FILL WITH BOUNDARY COMPENSATION

TIMING ANALYSIS FOR NON-SCAN LATCHES

Framework for hierarchical VLSI design