Kun Xu

DMA operations using dual tail pointers

Direct memory access operation for neural network accelerator

Congestion aware placement of fabric components

Overhead reduction using address translation in direct memory accesses

Memory page error tracking

Feature-map throughput during training process

Physically aware design of interconnect fabric

Strong ordered transaction for DMA transfers

Distributive training with multicast

Matrix transpose hardware acceleration

Matrix transpose hardware acceleration

Multidimensional and multiblock tensorized direct memory access descriptors

Direct memory access operation for neural network accelerator

Address generation for page collision prevention

Address generation for page collision prevention in memory regions

Matrix transpose hardware acceleration

Tensorized direct memory access descriptors

Data replication for accelerator

Programmable computations in direct memory access engine

Sparse machine learning acceleration

Powering-down or rebooting a device in a system fabric

GRADIENT COMPRESSION FOR DISTRIBUTED TRAINING

Communication of data between software applications

Powering-down or rebooting a device in a system fabric

PCI-based bus system having peripheral device address translation based on base address register (BAR) index

Communication protocols in integrated systems

Interconnect distributed virtual memory (DVM) message preemptive responding

Avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols

Maintaining cache coherency using conditional intervention among multiple master devices

System and method for conditional task switching during ordering scope transitions

Low Latency Data Delivery

Systems and methods for direct memory access coherency among multiple processing cores

System and method for assigning memory access transfers between communication channels

System and method for transferring data between components of a data processor

System and method for maintaining packet order in an ordered data stream

System and method for assigning a message

System and method for direct memory access buffer utilization by setting DMA controller with plurality of arbitration weights associated with different DMA engines

Controller for managing a reset of a subset of threads in a multi-thread system

Message passing using direct memory access unit in a data processing system

Bandwidth control for a direct memory access unit within a data processing system

System and method for scalable movement and replication of data

Scheduling memory access requests using predicted memory timing and state information

Asynchronously scheduling memory access requests

Interconnect controller for a data processing device with transaction tag locking and method therefor

Technique for initializing data and instructions for core functional pattern generation in multi-core processor

Technique for generating hash-tuple independent of precedence order of applied rules

Programmable hash-tuple generation with parallel rule implementation independence

Trace buffer with a processor