Inventor profile of:

Jacob Botimer

City:

Ann Arbor, Michigan

Country:

United States

Published Applications:

18

Last publication date:

2026-01-29

Top Assignees for applications by Jacob Botimer

The entities that hold a legal rights for patent applications filed by inventor Botimer Jacob:

Recent patent applications by Botimer Jacob

Jacob Botimer from Ann Arbor, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-29
US20260030425A1
Physics

CHIPLET BASED COMPUTATIONAL ACCELERATORS AND CONFIGURATION METHODS

#2 | 2025-06-12
US20250190345A1
Physics

MEMORY PROCESSING UNIT ARCHITECTURES AND CONFIGURATIONS

#3 | 2025-01-30
US20250036566A1
Physics

MEMORY PROCESSING UNIT ARCHITECTURE MAPPING TECHNIQUES

#4 | 2025-01-30
US20250036565A1
Physics

MEMORY PROCESSING UNIT CORE ARCHITECTURES

#5 | 2024-08-15
US20240272821A1
Physics

CORE GROUP MEMORY PROCESSSING CHIP DESIGN

#6 | 2024-08-15
US20240272797A1
Physics

CORE GROUP MEMORY PROCESSING WITH MULTI-PRECISION WEIGHT PACKING

#7 | 2024-03-14
US20240086257A1
Physics

DIRECT DATAFLOW COMPUTE-IN-MEMORY ACCELERATOR INTERFACE AND ARCHITECTURE

#8 | 2023-09-28
US20230305807A1
Physics

CORE GROUP MEMORY PROCESSSING WITH MAC REUSE

#9 | 2023-08-31
US20230273729A1
Physics

CORE GROUP MEMORY PROCESSING WITH GROUP B-FLOAT ENCODING

#10 | 2023-08-17
US20230259282A1
Physics

CORE GROUP MEMORY PROCESSSING UNIT ARCHITECTURES AND CONFIGURATIONS

#11 | 2023-03-09
US20230076473A1
Physics

Memory processing unit architecture mapping techniques

#12 | 2023-03-09
US20230075069A1
Physics

Memory processing unit architectures and configurations

#13 | 2023-03-09
US20230073012A1
Physics

MEMORY PROCESSING UNIT CORE ARCHITECTURES

#14 | 2023-03-09
US20230072556A1
Physics

PROCESSING UNIT ARCHITECTURES AND TECHNIQUES FOR REUSABLE INSTRUCTIONS AND DATA

#15 | 2023-03-02
US20230061711A1
Physics

INTER-LAYER COMMUNICATION TECHNIQUES FOR MEMORY PROCESSING UNIT ARCHITECTURES

#16 | 2022-06-16
US20220188492A1
Physics

CHIPLET BASED ARTIFICIAL INTELLIGENCE ACCELERATORS AND CONFIGURATION METHODS

#17 | 2021-01-14
US20210011863A1
Physics

Non-volatile memory based processors and dataflow techniques

#18 | 2021-01-14
US20210011732A1
Physics

Matrix Data Reuse Techniques in Processing Systems

InventorID:

4975642 ⎘