Jon Scott Choy

TEMPERATURE SENSOR IMPLEMENTED WITH A MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM)

PARTITIONED NON-VOLATILE MEMORY (NVM) HAVING A NORMAL READ BUS AND A VERIFY READ BUS

Partitioned non-volatile memory (NVM) having a normal read bus and a verify read bus

Memory with one-time programmable (OTP) cells

Column repair in a memory system using a repair cache

Magnetoresistive random access memory (MRAM) with end of life margin sensor

Testing disruptive memories

Memory read circuitry with a flipped voltage follower

Non-volatile memory having write detect circuitry

Memory with one-time programmable (OTP) cells and reading operations thereof

Memory with sense amplifiers

Memory with cells having multiple select transistors

Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation

Non-volatle memory with virtual ground voltage provided to unselected column lines during memory read operation

Memory with select line voltage control

Non-volatile memory with multiplexer transistor regulator circuit

Non-volatile memory with a well bias generation circuit

Non-volatile memory with selectable hard write

Reference generation for voltage sensing in a resistive memory

Magnetoresistive random access memory (MRAM) with OTP cells

Non-volatile memory with a select gate regulator circuit

Voltage sampling switch

Memory with a global reference circuit

Sense amplifier circuit

Sense amplifier circuit