Inventor profile of:

Alfred Haeusler

City:

Freising

Country:

Germany

Published Applications:

16

Last publication date:

2013-10-24

Top Assignees for applications by Alfred Haeusler

The entities that hold a legal rights for patent applications filed by inventor Haeusler Alfred:

Recent patent applications by Haeusler Alfred

Alfred Haeusler from Freising, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-10-24
US20130280906A1
Electricity

SEMICONDUCTOR DEVICE INCLUDING A DEEP CONTACT AND A METHOD OF MANUFACTURING SUCH A DEVICE

#2 | 2013-05-30
US20130134531A1
Performing operations; transporting

Fully embedded micromechanical device, system on chip and method for manufacturing the same

#3 | 2012-08-16
US20120205775A1
Electricity

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE

#4 | 2012-06-28
US20120164802A1
Electricity

Advanced CMOS using super steep retrograde wells

#5 | 2011-05-12
US20110111553A1
Electricity

Advanced CMOS using super steep retrograde wells

#6 | 2011-03-24
US20110070719A1
Electricity

Tuning of SOI substrate doping

#7 | 2010-11-11
US20100283119A1
Electricity

Semiconductor device including a deep contact and a method of manufacturing such a device

#8 | 2010-06-17
US20100148308A1
Electricity

Dopant Profile Control for Ultrashallow Arsenic Dopant Profiles

#9 | 2009-08-27
US20090212393A1
Electricity

Method of manufacturing an electronic device including a PNP bipolar transistor

#10 | 2009-05-21
US20090130805A1
Electricity

Advanced CMOS using super steep retrograde wells

#11 | 2008-06-05
US20080132012A1
Electricity

Advanced CMOS using super steep retrograde wells

#12 | 2006-09-07
US20060197158A1
Electricity

Advanced CMOS using super steep retrograde wells

#13 | 2006-08-10
US20060175657A1
Electricity

Advanced CMOS using super steep retrograde wells

#14 | 2006-06-20
US9948856
-

Advanced CMOS using super steep retrograde wells

#15 | 2005-05-12
US20050098093A1
Chemistry; metallurgy

Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer

#16 | 2005-01-06
US20050001236A1
Electricity

Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor

InventorID:

497858 ⎘