Inventor profile of:

John Paul Strachan

City:

Milpitas, California

Country:

United States

Published Applications:

15

Last publication date:

2023-08-03

Top Assignees for applications by John Paul Strachan

The entities that hold a legal rights for patent applications filed by inventor Strachan John Paul:

Recent patent applications by Strachan John Paul

John Paul Strachan from Milpitas, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-08-03
US20230246655A1
Electricity

Analog error detection and correction in analog in-memory crossbars

#2 | 2023-06-22
US20230197151A1
Physics

CAMs for low latency complex distribution sampling

#3 | 2023-05-04
US20230137079A1
Physics

Iterative programming of analog content addressable memory

#4 | 2023-01-19
US20230019942A1
Physics

Quantum-inspired algorithms to solve intractable problems using classical computers

#5 | 2022-11-24
US20220375536A1
Physics

Analog content addressable memory for storing and searching arbitrary segments of ranges

#6 | 2022-11-03
US20220351794A1
Physics

Analog content addressable memory with analog input and analog output

#7 | 2022-05-05
US20220138204A1
Physics

Accelerating constrained, flexible, and optimizable rule look-ups in hardware

#8 | 2022-04-21
US20220122646A1
Physics

Hardware accelerator with analog-content addressable memory (a-CAM) for decision tree computation

#9 | 2022-03-03
US20220069541A1
Electricity

Semiconductor laser diode integrated with memristor

#10 | 2021-08-05
US20210241068A1
Physics

CONVOLUTIONAL NEURAL NETWORK

#11 | 2021-08-05
US20210240945A1
Physics

Resistive and digital processing cores

#12 | 2021-07-01
US20210201136A1
Physics

Acceleration of model/weight programming in memristor crossbar arrays

#13 | 2021-02-18
US20210049125A1
Physics

Methods and systems for computing in memory

#14 | 2021-02-04
US20210036058A1
Electricity

Vertical JFET device for memristor array interface

#15 | 2021-01-21
US20210021620A1
Electricity

UPDATING REGULAR EXPRESSION PATTERN SET IN TERNARY CONTENT-ADDRESSABLE MEMORY

InventorID:

4983352 ⎘