Inventor profile of:

Thomas Mark Ulrich

City:

Mountain View, California

Country:

United States

Published Applications:

19

Last publication date:

2024-03-21

Top Assignees for applications by Thomas Mark Ulrich

The entities that hold a legal rights for patent applications filed by inventor Ulrich Thomas Mark:

Recent patent applications by Ulrich Thomas Mark

Thomas Mark Ulrich from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-03-21
US20240095304A1
Physics

FLEXIBLE MATRIX PROCESSING

#2 | 2023-03-07
US16725331
Physics

Systems and methods for reducing power consumption of convolution operations of artificial neural networks

#3 | 2022-11-17
US20220365784A1
Physics

MATRIX PROCESSING INSTRUCTION WITH OPTIONAL UP/DOWN SAMPLING OF MATRIX

#4 | 2022-04-07
US20220107782A1
Physics

FLOATING POINT MULTIPLY HARDWARE USING DECOMPOSED COMPONENT NUMBERS

#5 | 2021-11-11
US20210349965A1
Physics

Device and method for flexibly summing matrix values

#6 | 2021-11-11
US20210349694A1
Physics

Bypassing zero-value multiplications in a hardware multiplier

#7 | 2021-11-11
US20210349690A1
Physics

Using a low-bit-width dot product engine to sum high-bit-width numbers

#8 | 2021-10-28
US20210334072A1
Physics

MAPPING CONVOLUTION TO CONNECTED PROCESSING ELEMENTS USING DISTRIBUTED PIPELINED SEPARABLE CONVOLUTION OPERATIONS

#9 | 2021-10-14
US20210319076A1
Physics

Grouped convolution using point-to-point connected channel convolution engines

#10 | 2021-09-23
US20210294875A1
Physics

Pipelined pointwise convolution using per-channel convolution operations

#11 | 2021-09-02
US20210271451A1
Physics

Mapping convolution to a partition channel convolution engine

#12 | 2021-08-19
US20210256363A1
Physics

Mapping convolution to a channel convolution engine

#13 | 2021-08-19
US20210255830A1
Physics

Hardware for floating-point arithmetic in multiple formats

#14 | 2021-06-10
US20210173646A1
Physics

Matrix processing instruction with optional up/down sampling of matrix

#15 | 2021-04-29
US20210125044A1
Physics

Support for different matrix multiplications by selecting adder tree intermediate results

#16 | 2021-04-29
US20210124794A1
Physics

High throughput matrix processor with support for concurrently processing multiple matrices

#17 | 2021-04-08
US20210103429A1
Physics

Floating point multiply hardware using decomposed component numbers

#18 | 2021-03-11
US20210073316A1
Physics

NUMBER-THEORETIC TRANSFORM HARDWARE

#19 | 2021-01-28
US20210026916A1
Physics

Matrix multiplication in hardware using modular math

InventorID:

4987571 ⎘