Vilas, North Carolina
United States
39
2014-08-21
The entities that hold a legal rights for patent applications filed by inventor Barry Edwin Franklin:
Edwin Franklin Barry from Vilas, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Methods and apparatus for scalable array processor interrupt detection and response
#2 | 2014-04-29Methods and apparatus for address translation functions
#3 | 2014-03-13Methods and apparatus for adapting pipeline stage latency based on instruction type
#4 | 2014-03-13Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
#5 | 2014-02-27System core for transferring data between an external device and memory
#6 | 2013-10-24Methods and apparatus for scalable array processor interrupt detection and response
#7 | 2013-01-03System core for transferring data between an external device and memory
#8 | 2012-12-27Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
#9 | 2012-07-05Methods and apparatus for scalable array processor interrupt detection and response
#10 | 2012-05-24Methods and apparatus for independent processor node operations in a SIMD array processor
#11 | 2012-05-17System core for transferring data between an external device and memory
#12 | 2012-01-24Methods and apparatus for independent processor node operations in a SIMD array processor
#13 | 2011-12-08Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
#14 | 2011-09-15Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
#15 | 2011-09-01Methods and apparatus for address translation functions
#16 | 2011-06-23Methods and apparatus for providing data transfer control
#17 | 2011-05-17Methods and apparatus for address translation functions
#18 | 2011-03-24Methods and apparatus for scalable array processor interrupt detection and response
#19 | 2010-12-16Methods and apparatus for adapting pipeline stage latency based on instruction type
#20 | 2010-10-07Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
#21 | 2010-10-05Methods and apparatus for adapting pipeline stage latency based on instruction type
#22 | 2009-12-03Methods and apparatus for providing data transfer control
#23 | 2008-09-11Methods and apparatus for scalable array processor interrupt detection and response
#24 | 2008-06-05Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions
#25 | 2008-03-06Methods and apparatus for providing data transfer control
#26 | 2008-02-21Methods and apparatus for independent processor node operations in a SIMD array processor
#27 | 2008-01-17Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
#28 | 2007-09-18Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques
#29 | 2007-09-04System core for transferring data between an external device and memory
#30 | 2007-08-14Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions
#31 | 2007-06-26Methods and apparatus for providing context switching between software tasks with reconfigurable control
#32 | 2007-04-19Methods and apparatus for providing data transfer control
#33 | 2006-12-05Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
#34 | 2006-06-01Coprocessor processing instructions in turn from multiple instruction ports coupled to respective processors
#35 | 2005-08-04Methods and apparatus for providing data transfer control
#36 | 2005-06-28Methods and apparatus for pipelined bus
#37 | 2005-06-09Cascaded event detection modules for generating combined events interrupt for processor action
#38 | 2005-02-03Methods and apparatus for scalable array processor interrupt detection and response
#39 | 2005-02-01Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
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