Inventor profile of:

Krishnakumar Narayanan Nair

City:

Newark, California

Country:

United States

Published Applications:

28

Last publication date:

2024-03-21

Top Assignees for applications by Krishnakumar Narayanan Nair

The entities that hold a legal rights for patent applications filed by inventor Nair Krishnakumar Narayanan:

Recent patent applications by Nair Krishnakumar Narayanan

Krishnakumar Narayanan Nair from Newark, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-03-21
US20240095304A1
Physics

FLEXIBLE MATRIX PROCESSING

#2 | 2023-09-19
US17396555
Physics

Systems and methods for reducing power consumption of convolution operations for artificial neural networks

#3 | 2023-08-10
US20230251903A1
Physics

HIGH BANDWIDTH MEMORY SYSTEM WITH DYNAMICALLY PROGRAMMABLE DISTRIBUTION SCHEME

#4 | 2023-03-07
US16725331
Physics

Systems and methods for reducing power consumption of convolution operations of artificial neural networks

#5 | 2023-02-23
US20230056304A1
Physics

USING A LOW-BIT-WIDTH DOT PRODUCT ENGINE TO SUM HIGH-BIT-WIDTH NUMBERS

#6 | 2023-01-05
US20230004624A1
Physics

HIGH THROUGHPUT MATRIX PROCESSOR WITH SUPPORT FOR CONCURRENTLY PROCESSING MULTIPLE MATRICES

#7 | 2022-11-24
US20220374499A1
Physics

Device and method for flexibly summing matrix values

#8 | 2022-11-17
US20220365784A1
Physics

MATRIX PROCESSING INSTRUCTION WITH OPTIONAL UP/DOWN SAMPLING OF MATRIX

#9 | 2022-11-15
US16777606
Physics

Systems and methods for handling padding regions in convolution operations

#10 | 2022-04-07
US20220107782A1
Physics

FLOATING POINT MULTIPLY HARDWARE USING DECOMPOSED COMPONENT NUMBERS

#11 | 2021-11-11
US20210349965A1
Physics

Device and method for flexibly summing matrix values

#12 | 2021-11-11
US20210349690A1
Physics

Using a low-bit-width dot product engine to sum high-bit-width numbers

#13 | 2021-10-28
US20210334072A1
Physics

MAPPING CONVOLUTION TO CONNECTED PROCESSING ELEMENTS USING DISTRIBUTED PIPELINED SEPARABLE CONVOLUTION OPERATIONS

#14 | 2021-10-21
US20210326051A1
Physics

High bandwidth memory system with distributed request broadcasting masters

#15 | 2021-10-14
US20210319076A1
Physics

Grouped convolution using point-to-point connected channel convolution engines

#16 | 2021-09-23
US20210294875A1
Physics

Pipelined pointwise convolution using per-channel convolution operations

#17 | 2021-09-02
US20210271451A1
Physics

Mapping convolution to a partition channel convolution engine

#18 | 2021-08-19
US20210256363A1
Physics

Mapping convolution to a channel convolution engine

#19 | 2021-08-19
US20210255830A1
Physics

Hardware for floating-point arithmetic in multiple formats

#20 | 2021-06-24
US20210192359A1
Physics

Systems and methods for reducing data movement during convolution operations in artificial neural networks

#21 | 2021-06-17
US20210182196A1
Physics

High bandwidth memory system with crossbar switch for dynamically programmable distribution scheme

#22 | 2021-06-17
US20210181957A1
Physics

High bandwidth memory system with distributed request broadcasting masters

#23 | 2021-06-10
US20210173646A1
Physics

Matrix processing instruction with optional up/down sampling of matrix

#24 | 2021-06-03
US20210165691A1
Physics

High bandwidth memory system with dynamically programmable distribution scheme

#25 | 2021-04-29
US20210125044A1
Physics

Support for different matrix multiplications by selecting adder tree intermediate results

#26 | 2021-04-29
US20210124794A1
Physics

High throughput matrix processor with support for concurrently processing multiple matrices

#27 | 2021-04-08
US20210103429A1
Physics

Floating point multiply hardware using decomposed component numbers

#28 | 2020-12-22
US16588859
Physics

Memory organization for matrix processing

InventorID:

5047994 ⎘