Lagrangeville, New York
United States
38
2018-05-10
The entities that hold a legal rights for patent applications filed by inventor Greco Stephen E.:
Stephen E. Greco from Lagrangeville, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Early overlay prediction and overlay-aware mask design
#2 | 2017-09-28Multiple-depth trench interconnect technology at advanced semiconductor nodes
#3 | 2016-12-29Early overlay prediction and overlay-aware mask design
#4 | 2016-06-23Dividing lithography exposure fields to improve semiconductor fabrication
#5 | 2016-02-11Multiple-depth trench interconnect technology at advanced semiconductor nodes
#6 | 2016-01-28Interconnect level structures for confining stitch-induced via structures
#7 | 2015-11-26Stitch-derived via structures and methods of generating the same
#8 | 2015-09-10Selective local metal cap layer formation for improved electromigration behavior
#9 | 2015-09-10Selective local metal cap layer formation for improved electromigration behavior
#10 | 2015-09-10Selective local metal cap layer formation for improved electromigration behavior
#11 | 2015-05-21Reticle data decomposition for focal plane determination in lithographic processes
#12 | 2014-09-25Interconnect level structures for confining stitch-induced via structures
#13 | 2014-08-12Generation of design shapes for confining stitch-induced via structures
#14 | 2014-07-24Selective local metal cap layer formation for improved electromigration behavior
#15 | 2014-05-22Measuring metal line spacing in semiconductor devices
#16 | 2013-10-31System and method of predicting problematic areas for lithography in a circuit design
#17 | 2012-10-04System and method of predicting problematic areas for lithography in a circuit design
#18 | 2012-06-28IC having viabar interconnection and related method
#19 | 2011-07-28System and method of predicting problematic areas for lithography in a circuit design
#20 | 2010-03-25Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design
#21 | 2010-02-11IC having viabar interconnection and related method
#22 | 2010-02-04Via density change to improve wafer surface planarity
#23 | 2009-10-22System and method of predicting problematic areas for lithography in a circuit design
#24 | 2009-10-22Intersect area based ground rule for semiconductor design
#25 | 2008-07-31Integrated circuit fuse
#26 | 2008-06-24Integrated circuit fuse and method of opening
#27 | 2008-04-17Dry etchback of interconnect contacts
#28 | 2008-01-31Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via
#29 | 2007-07-19Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors
#30 | 2007-05-31Laser fuse structures for high power applications
#31 | 2007-04-19Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via
#32 | 2007-02-08Dry etchback of interconnect contacts
#33 | 2006-11-02Dynamic metal fill for correcting non-planar region
#34 | 2006-07-04Forming of local and global wiring for semiconductor product
#35 | 2005-09-15Method to generate porous organic dielectric
#36 | 2005-07-26Method to generate porous organic dielectric
#37 | 2005-07-12Reliable low-k interconnect structure with hybrid dielectric
#38 | 2005-02-03Reliable low-k interconnect structure with hybrid dielectric
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