Inventor profile of:

Mark McDermott

City:

Austin, Texas

Country:

United States

Published Applications:

19

Last publication date:

2026-01-01

Top Assignees for applications by Mark McDermott

The entities that hold a legal rights for patent applications filed by inventor McDermott Mark:

Recent patent applications by McDermott Mark

Mark McDermott from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-01
US20260005069A1
Electricity

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

#2 | 2026-01-01
US20260005060A1
Electricity

HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING MOIRÉ BASED METROLOGY AND VACUUM BASED PICK-AND-PLACE

#3 | 2026-01-01
US20260004037A1
Physics

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE ASICS

#4 | 2026-01-01
US20260004036A1
Physics

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE ASICS

#5 | 2025-12-18
US20250385135A1
Electricity

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

#6 | 2025-12-18
US20250385134A1
Electricity

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

#7 | 2025-12-18
US20250385121A1
Electricity

HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING MOIRÉ BASED METROLOGY AND VACUUM BASED PICK-AND-PLACE

#8 | 2025-12-18
US20250385120A1
Electricity

HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING MOIRÉ BASED METROLOGY AND VACUUM BASED PICK-AND-PLACE

#9 | 2025-09-11
US20250285904A1
Electricity

HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING MOIRÉ BASED METROLOGY AND VACUUM BASED PICK-AND-PLACE

#10 | 2024-12-26
US20240429099A1
Electricity

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

#11 | 2024-10-03
US20240332056A1
Electricity

Heterogeneous integration of components onto compact devices using moiré based metrology and vacuum based pick-and-place

#12 | 2023-12-28
US20230419010A1
Physics

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE ASICS

#13 | 2023-04-20
US20230124676A1
Physics

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE ASICS

#14 | 2023-04-20
US20230118578A1
Physics

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE ASICS

#15 | 2023-04-13
US20230116581A1
Electricity

Nanoscale-aligned three-dimensional stacked integrated circuit

#16 | 2023-02-09
US20230042873A1
Electricity

Heterogeneous integration of components onto compact devices using moiré based metrology and vacuum based pick-and-place

#17 | 2021-11-25
US20210366771A1
Electricity

Nanoscale-aligned three-dimensional stacked integrated circuit

#18 | 2021-11-11
US20210350061A1
Physics

Nanofabrication and design techniques for 3D ICs and configurable ASICs

#19 | 2021-05-06
US20210134640A1
Electricity

Heterogeneous integration of components onto compact devices using moire based metrology and vacuum based pick-and-place

InventorID:

5073232 ⎘