Plano, Texas
United States
44
2022-04-21
The entities that hold a legal rights for patent applications filed by inventor Bartling Steven Craig:
Steven Craig Bartling from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Nonvolatile logic memory for computing module reconfiguration
#2 | 2022-04-14Customizable backup and restore from nonvolatile logic array
#3 | 2021-12-02Compute through power loss hardware approach for processing device having nonvolatile logic memory
#4 | 2020-04-30Processing device with nonvolatile logic array backup
#5 | 2020-04-23Nonvolatile logic memory for computing module reconfiguration
#6 | 2019-12-12Compute through power loss hardware approach for processing device having nonvolatile logic memory
#7 | 2019-02-07Processing device with nonvolatile logic array backup
#8 | 2018-06-21Priority based backup in nonvolatile logic arrays
#9 | 2017-11-09Nonvolatile logic array based computing over inconsistent power supply
#10 | 2017-10-05Configuration bit sequencing control of nonvolatile domain and array wakeup and backup
#11 | 2017-06-29Compute through power loss hardware approach for processing device having nonvolatile logic memory
#12 | 2017-04-20Nonvolatile logic memory for computing module reconfiguration
#13 | 2016-08-25Compute through power loss approach for processing device having nonvolatile logic memory
#14 | 2016-07-28Customizable backup and restore from nonvolatile logic array
#15 | 2015-03-26Non-volatile logic based processing device
#16 | 2015-03-05Dual-port negative level sensitive data retention latch
#17 | 2015-02-26Dual-port negative level sensitive reset data retention latch
#18 | 2014-07-31Nonvolatile logic array with built-in test drivers
#19 | 2014-07-31Nonvolatile logic array with built-in test result signal
#20 | 2014-07-31Two capacitor self-referencing nonvolatile bitcell
#21 | 2014-07-31Four capacitor nonvolatile bit cell
#22 | 2014-07-31Signal level conversion in nonvolatile bitcell array
#23 | 2014-07-31Error detection in nonvolatile logic arrays using parity
#24 | 2014-03-13Customizable backup and restore from nonvolatile logic array
#25 | 2014-03-13Nonvolatile backup of a machine state when a power supply drops below a threshhold
#26 | 2014-03-13Non-volatile array wakeup and backup sequencing control
#27 | 2014-03-13Nonvolatile logic array and power domain segmentation in processing device
#28 | 2014-03-13Control of Dedicated Non-Volatile Arrays for Specific Function Availability
#29 | 2014-03-13Boot State Restore from Nonvolatile Bitcell Array
#30 | 2014-03-13Processing Device With Restricted Power Domain Wakeup Restore From Nonvolatile Logic Array
#31 | 2014-03-13Configuration bit sequencing control of nonvolatile domain and array wakeup and backup
#32 | 2014-03-13Nonvolatile logic array with retention flip flops to reduce switching power during wakeup
#33 | 2014-03-13Processing device with nonvolatile logic array backup
#34 | 2014-03-13Priority based backup in nonvolatile logic arrays
#35 | 2013-11-28Integrated circuit with integrated decoupling capacitors
#36 | 2013-03-14Integrated circuit with integrated decoupling capacitors
#37 | 2013-01-24Differential plate line screen test for ferroelectric latch circuits
#38 | 2012-08-02Differential plate line screen test for ferroelectric latch circuits
#39 | 2012-07-05Method and apparatus pertaining to a ferroelectric random access memory
#40 | 2012-07-05Method and apparatus pertaining to a ferroelectric random access memory
#41 | 2012-07-05Ferroelectric memory with shunt device
#42 | 2012-07-05Ferroelectric memory write-back
#43 | 2012-07-05Ferroelectric Memory Electrical Contact
#44 | 2010-11-25Differential plate line screen test for ferroelectric latch circuits
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