Xiaowei Deng

Sense amplifier look-through latch for FAMOS-based EPROM

Array power supply-based screening of static random access memory cells for bias temperature instability

Array power supply-based screening of static random access memory cells for bias temperature instability

Array power supply-based screening of static random access memory cells for bias temperature instability

Array power supply-based screening of static random access memory cells for bias temperature instability

SRAM with buffered-read bit cells and its testing

STATIC RANDOM ACCESS MEMORY CELL WITH SINGLE-SIDED BUFFER AND ASYMMETRIC CONSTRUCTION

SRAM WITH BUFFERED-READ BIT CELLS AND ITS TESTING

Static random-access memory cell array with deep well regions

Reducing power in SRAM using supply voltage control

Efficient static random-access memory layout

Static random access memory cell with single-sided buffer and asymmetric construction

Functional screening of static random access memories using an array bias voltage

DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL

Array-based integrated circuit with reduced proximity effects

Method of screening static random access memories for unstable memory cells

Array power supply-based screening of static random access memory cells for bias temperature instability

Solid-state memory cell with improved read stability

Array-based integrated circuit with reduced proximity effects

SRAM with buffered-read bit cells and its testing

Memory cell with equalization write assist in solid-state memory

Disturb-free static random access memory cell

Bit-by-bit write assist for solid-state memory

Margin testing of static random access memory cells

Universal test structures based SRAM on-chip parametric test module and methods of operating and testing

UNIVERSAL STRUCTURE FOR MEMORY CELL CHARACTERIZATION

Structure and methods for measuring margins in an SRAM bit

METHOD FOR MEMORY CELL CHARACTERIZATION USING UNIVERSAL STRUCTURE

Method and structure for SRAM cell trip voltage measurement

Method and structure for SRAM Vmin/Vmax measurement

Structure and method for screening SRAMS

Method for constructing Shmoo plots for SRAMs

Structure and methods for measuring margins in an SRAM bit

Mitigation of charge sharing in memory devices

Bitline leakage detection in memories

Characterization of bits in a functional memory

Memory cell layout structure with outer bitline

Method for memory cell characterization using universal structure

Universal structure for memory cell characterization

Method for testing transistors having an active region that is common with other transistors and a testing circuit for accomplishing the same

SRAM cell with column select line

Low leakage SRAM scheme

Bit line control for low power in standby

Static logic design for CMOS

Leakage current reduction method

Bit line control for low power in standby

High performance SRAM device and method of powering-down the same

SRAM device and a method of powering-down the same

System and method for measuring a capacitance associated with an integrated circuit

Voltage keeping scheme for low-leakage memory devices

System for reducing row periphery power consumption in memory devices

System for reducing row periphery power consumption in memory devices