Greater Noida
India
37
2026-06-18
The entities that hold a legal rights for patent applications filed by inventor KUMAR Promod:
Promod KUMAR from Greater Noida, IN has applied for patents for these inventions. The list has both pending applications and granted patents:
ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEMORY ARCHITECTURE
#2 | 2026-03-05SHADOW LOGIC ON OUTPUT, AT SPEED TEST (MEMORY BYPASS) ARCHITECTURE FOR MEMORIES WITHOUT INPUT DATA
#3 | 2026-03-05ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPERATION BY ACCOUNTING FOR VARIATION IN READ CURRENT
#4 | 2026-03-05BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)
#5 | 2026-01-29MEMORY ARCHITECTURE WITH A DIGITAL IN-MEMORY COMPUTATION PROCESSING MODE AND A COLUMN MULTIPLEXING MEMORY ACCESS MODE
#6 | 2026-01-15AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK MEMORY
#7 | 2025-10-02ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)
#8 | 2025-05-29SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)
#9 | 2025-03-06BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
#10 | 2025-02-27BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY INPUT/OUTPUT
#11 | 2025-02-13SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESET, AND DATA CORRUPTION MODES FOR SECURE APPLICATIONS
#12 | 2025-02-13SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESET, AND DATA CORRUPTION MODES FOR SECURE APPLICATIONS
#13 | 2024-11-28SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULATION FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)
#14 | 2024-05-30BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT
#15 | 2024-05-02TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDENT ON OPERATIONAL MODE SELECTION
#16 | 2024-04-04AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK MEMORY
#17 | 2024-04-04ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEMORY ARCHITECTURE
#18 | 2024-02-29Built-in self test circuit for segmented static random access memory (SRAM) array input/output
#19 | 2024-02-29MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE AND DIGITAL IN-MEMORY COMPUTATION PROCESSING MODE
#20 | 2024-02-29MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE AND DIGITAL IN-MEMORY COMPUTATION PROCESSING MODE
#21 | 2024-02-29BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY INPUT/OUTPUT
#22 | 2024-01-11SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH A STATIC RANDOM ACCESS MEMORY CIRCUIT
#23 | 2023-12-21BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)
#24 | 2023-12-21IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY SEGMENTATION
#25 | 2023-11-30BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)
#26 | 2023-11-30IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY SEGMENTATION AND LOCAL COMPUTE TILE READ BASED ON WEIGHTED CURRENT
#27 | 2023-11-30ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPERATION BY ACCOUNTING FOR VARIATION IN READ CURRENT
#28 | 2023-11-02Computing system power management device, system and method
#29 | 2023-03-30Bit-cell architecture based in-memory compute
#30 | 2023-02-16Modular memory architecture with gated sub-array operation dependent on stored data content
#31 | 2023-01-19SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications
#32 | 2023-01-19Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
#33 | 2023-01-12Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
#34 | 2023-01-12Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
#35 | 2023-01-12Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
#36 | 2023-01-12ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)
#37 | 2021-06-17Computing system power management device, system and method
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