Inventor profile of:

Ching-Wei WU

City:

Hsinchu

Country:

Taiwan

Published Applications:

28

Last publication date:

2026-06-18

Top Assignees for applications by Ching-Wei WU

The entities that hold a legal rights for patent applications filed by inventor WU Ching-Wei:

Recent patent applications by WU Ching-Wei

Ching-Wei WU from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-06-18
US20260170220A1
Physics

MEMORY WITH BUNDLE-WIDE ACCESS LINES, METHOD OF READING FROM THE SAME AND METHOD OF MANUFACTURING SAME

#2 | 2025-11-27
US20250364023A1
Physics

MEMORY DEVICE HAVING TRACKING WORD LINE WITH ADJUST CIRCUIT AND METHOD OF OPERATING SAME

#3 | 2025-11-20
US20250356886A1
Physics

CIRCUIT AND METHOD FOR POWER MANAGEMENT

#4 | 2025-11-13
US20250349347A1
Physics

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

#5 | 2025-11-13
US20250349339A1
Physics

MEMORY DEVICES CONFIGURED WITH ADAPTIVE WORD LINE PULSE ADJUSTMENT AND METHODS FOR OPERATING THE SAME

#6 | 2025-10-23
US20250329381A1
Physics

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

#7 | 2025-09-25
US20250299725A1
Physics

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

#8 | 2025-07-10
US20250226012A1
Physics

CIRCUIT AND METHOD FOR POWER MANAGEMENT

#9 | 2025-05-15
US20250157512A1
Physics

MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME

#10 | 2025-05-08
US20250149070A1
Physics

CIRCUIT AND METHOD OF OPERATING THE SAME

#11 | 2025-05-01
US20250140294A1
Physics

SHARED DECODER CIRCUIT AND METHOD

#12 | 2025-03-20
US20250095704A1
Physics

MEMORY DEVICE HAVING TRACKING WORD LINE WITH ADJUST CIRCUIT, METHOD OF OPERATING SAME AND METHOD OF MANUFACTURING SAME

#13 | 2025-01-30
US20250037751A1
Physics

MEMORY DEVICES CONFIGURED WITH ADAPTIVE WORD LINE PULSE ADJUSTMENT AND METHODS FOR OPERATING THE SAME

#14 | 2025-01-09
US20250014659A1
Physics

READ-ONLY MEMORY METHOD, LAYOUT, AND DEVICE

#15 | 2025-01-02
US20250006255A1
Physics

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

#16 | 2024-10-24
US20240355374A1
Physics

MEMORY CIRCUITS WITH DYNAMICALLY ADJUSTABLE PULSE WIDTHS AND METHODS FOR OPERATING THE SAME

#17 | 2023-11-23
US20230378939A1
Electricity

Latch circuit and memory device

#18 | 2023-11-16
US20230368828A1
Physics

Shared decoder circuit and method

#19 | 2023-11-16
US20230368826A1
Physics

Memory circuit and method of operating the same

#20 | 2023-04-13
US20230114646A1
Physics

Circuit and method of operating the same

#21 | 2022-11-24
US20220375512A1
Physics

Shared decoder circuit and method

#22 | 2022-11-17
US20220366950A1
Physics

Memory circuit and method of operating the same

#23 | 2022-09-01
US20220277781A1
Physics

Memory circuit and method of operating the same

#24 | 2022-06-23
US20220199124A1
Physics

Circuit and method of operating the same

#25 | 2022-06-16
US20220189542A1
Physics

Circuit and method of writing to a bit cell

#26 | 2022-03-03
US20220069807A1
Electricity

Latch circuit, memory device and method

#27 | 2021-12-09
US20210383052A1
Physics

Method of certifying safety levels of semiconductor memories in integrated circuits

#28 | 2021-06-17
US20210183423A1
Physics

Shared decoder circuit and method

InventorID:

5111363 ⎘