Robert T. Golla

Adaptive microprocessor power ramp control

MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR USING A GENERAL LOAD/STORE TIMEOUT COUNTER

Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load miss

Multi-threaded instruction buffer design

Hybrid instruction buffer

Handling multi-cycle integer operations for a multi-threaded processor

Method and system for sharing functional units of a multithreaded processor

Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations

Mechanism for selecting instructions for execution in a multithreaded processor

Method for selecting between divide instructions associated with respective threads in a multi-threaded processor

Apparatus and method for local operand bypassing for cryptographic instructions

Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor

Optimal deallocation of instructions from a unified pick queue

Accessing a multibank register file using a thread identifier

Dynamic mitigation of thread hogs on a threaded processor

Dynamic tag allocation in a multithreaded out-of-order processor

Dependency matrix for the determination of load dependencies

Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructions

System and method to manage address translation requests

Delay slot handling in a processor

System and method for balancing instruction loads between multiple execution units using assignment history

Processor and method for implementing instruction support for multiplication of large operands

System and method for out-of-order resource allocation and deallocation in a threaded machine

Single cycle data movement between general purpose and floating-point registers

Dynamic allocation of resources in a threaded, heterogeneous processor

Processor operating mode for mitigating dependency conditions between instructions having different operand sizes

Logical map table for detecting dependency conditions between instructions having varying width operand values

PHYSICALLY-INDEXED LOGICAL MAP TABLE

Methods and mechanisms to support multiple features for a number of opcodes

Processor and method for implementing instruction support for hash algorithms

Branch misprediction recovery mechanism for microprocessors

Register access protocol in a multihreaded multi-core processor

Memory with write port configured for double pump write

Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor

Efficient utilization of a store buffer using counters

Handling cache misses by selectively flushing the pipeline

Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor

Arbitration of window swap operations

Concurrent bypass to instruction buffers in a fine grain multithreaded processor

Minimal address state in a fine grain multithreaded processor

Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window

Fetch speculation in a multithreaded processor

Method and apparatus for power throttling in a multi-thread processor

Thread-based clock enabling in a multi-threaded processor

Apparatus and method for fine-grained multithreading in a multipipelined processor core

Mechanism for selecting instructions for execution in a multithreaded processor