Brian Michael Stempel

SELECTING A CANDIDATE CONSUMER INSTRUCTION BASED ON AN OBSERVED INSTRUCTION HAVING A DEPENDENCY MARKED SOURCE OPERAND FROM PRODUCER DATA OF A PRODUCER INSTRUCTION

PRODUCER-CONSUMER RELATIONSHIPS

Operand-based reach explicit dataflow processors, and related methods and computer-readable media

Method, apparatus, and system for memory bandwidth aware data prefetching

Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions

AGGREGATING CACHE MAINTENANCE INSTRUCTIONS IN PROCESSOR-BASED DEVICES

PRECISE INVALIDATION OF VIRTUALLY TAGGED CACHES

Dependency-prediction of instructions

Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems

ELIMINATING REDUNDANT SYNCHRONIZATION BARRIERS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA

Optimizing performance for context-dependent instructions

Method to improve speed of executing return branch instructions in a processor

METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPENDENT INSTRUCTIONS MORE EFFICIENTLY USING A CONSTANT CACHE

Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media

Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media

Methods and apparatus for managing page crossing instructions with different cacheability

FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA

Qualifying Software Branch-Target Hints with Hardware-Based Predictions

PREVENTING EXECUTION OF PARITY-ERROR-INDUCED UNPREDICTABLE INSTRUCTIONS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA

Multi level indirect predictor using confidence counter and program counter address filter scheme

Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media

Method and apparatus for tracking extra data permissions in an instruction cache

Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media

Link stack repair of erroneous speculative update

Link stack repair of erroneous speculative update

Preloading instructions from an instruction set other than a currently executing instruction set

Selective powering of a BHT in a processor having variable length instructions

Apparatus and methods for speculative interrupt vector prefetching

Methods and system for resolving simultaneous predicted branch instructions

Predecode repair cache for instructions that cross an instruction cache line

Link stack repair of erroneous speculative update

Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information

System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding

System, method and software to preload instructions from an instruction set other than one currently executing

System and method for using a working global history register

Effective use of a BHT in processor having variable length instruction set execution modes

Methods and system for resolving simultaneous predicted branch instructions

Apparatus for generating return address predictions for implicit and explicit subroutine calls

Debug circuit comparing processor instruction set operating mode

Associate Cached Branch Information with the Last Granularity of Branch instruction in Variable Length instruction Set

Method and apparatus for prefetching non-sequential instruction addresses

Sliding-window, block-based branch target address cache

Pre-decoding variable length instructions

Method and apparatus for repairing a link stack

Caching memory attribute indicators with cached memory data field

Method and apparatus for managing cache partitioning using a dynamic boundary

Method and apparatus for managing a link return stack

Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions

Caching instructions for a multiple-state processor

Handling cache miss in an instruction crossing a cache line boundary

Power saving methods and apparatus to selectively enable cache bits based on known processor state

Forward looking branch target address caching

Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions

Pre-decode error handling via branch correction