Michael L. Case

Formal verification of booth multipliers

Method and system for optimal diameter bounding of designs with complex feed-forward components

Constructing inductive counterexamples in a multi-algorithm verification framework

Method and system for optimal counterexample-guided proof-based abstraction

Logical circuit netlist reduction and model simplification using simulation results containing symbolic values

REACHABILITY ANALYSIS BY LOGICAL CIRCUIT SIMULATION FOR PROVIDING OUTPUT SETS CONTAINING SYMBOLIC VALUES

Enhancing redundancy removal with early merging

Enhancing redundancy removal with early merging

Efficiently determining Boolean satisfiability with lazy constraints

Efficiently determining boolean satisfiability with lazy constraints

Method and system for scalable reduction in registers with SAT-based resubstitution

Techniques for employing retiming and transient simplification on netlists that include memory arrays

Optimal correlated array abstraction

Array concatenation in an integrated circuit design

Eliminating, coalescing, or bypassing ports in memory array representations

Minimizing memory array representations for enhanced synthesis and verification

Enhanced analysis of array-based netlists via reparameterization

Enhanced analysis of array-based netlists via phase abstraction

Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Tracking array data contents across three-valued read and write operations

Techniques for analysis of logic designs with transient logic

Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design

Method and system for design simplification through implication-based analysis

Automated convergence of ternary simulation by saturation of deep gates

Method for scalable derivation of an implication-based reachable state set overapproximation

Scalable reduction in registers with SAT-based resubstitution