Hari Mony

Adaptive bug-search depth for simple and deep counterexamples

Adaptive bug-search depth for simple and deep counterexamples

Method for scalable liveness verification via abstraction refinement

System and program product for scalable liveness verification via abstraction refinement

Enhanced case-splitting based property checking

Enhanced case-splitting based property checking

Method and system for performing invariant-guided abstraction of a logic design

Method and system for optimal diameter bounding of designs with complex feed-forward components

Constructing inductive counterexamples in a multi-algorithm verification framework

Method and system for optimal counterexample-guided proof-based abstraction

Logical circuit netlist reduction and model simplification using simulation results containing symbolic values

REACHABILITY ANALYSIS BY LOGICAL CIRCUIT SIMULATION FOR PROVIDING OUTPUT SETS CONTAINING SYMBOLIC VALUES

Enhancing redundancy removal with early merging

Enhancing redundancy removal with early merging

Efficiently determining Boolean satisfiability with lazy constraints

Efficiently determining boolean satisfiability with lazy constraints

Method and system for scalable reduction in registers with SAT-based resubstitution

Techniques for employing retiming and transient simplification on netlists that include memory arrays

Optimal correlated array abstraction

Array concatenation in an integrated circuit design

Eliminating, coalescing, or bypassing ports in memory array representations

Minimizing memory array representations for enhanced synthesis and verification

Enhanced analysis of array-based netlists via reparameterization

Enhanced analysis of array-based netlists via phase abstraction

Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Tracking array data contents across three-valued read and write operations

Techniques for analysis of logic designs with transient logic

Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design

Trace containment detection of combinational designs via constraint-based uncorrelated equivalence checking

Automated convergence of ternary simulation by saturation of deep gates

Method, system and application for sequential cofactor-based analysis of netlists

Method and system for sequential netlist reduction through trace-containment

Automated use of uninterpreted functions in sequential equivalence

Method for scalable derivation of an implication-based reachable state set overapproximation

Scalable reduction in registers with SAT-based resubstitution

Incremental speculative merging

Sequential equivalence checking for asynchronous verification

Optimal simplification of constraint-based testbenches

Enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms

Computer program product for extending incremental verification of circuit design to encompass verification restraints

Performing minimization of input count during structural netlist overapproximation

Predicate-based compositional minimization in a verification environment

Using constraints in design verification

Method for heuristic preservation of critical inputs during sequential reparameterization

PERFORMING UTILIZATION OF TRACES FOR INCREMENTAL REFINEMENT IN COUPLING A STRUCTURAL OVERAPPROXIMATION ALGORITHM AND A SATISFIABILITY SOLVER

Predicate selection in bit-level compositional transformations

Method and system for performing target enlargement in the presence of constraints

Method and system for performing ternary verification

Generating constraint preserving testcases in the presence of dead-end constraints

Computer program product for design verification using sequential and combinational transformations

Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Incremental design reduction via iterative overapproximation and re-encoding strategies

Reversing the effects of sequential reparameterization on traces

Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Method and system for parametric reduction of sequential designs

Method and system for reversing the effects of sequential reparameterization on traces

Parametric reduction of sequential design

Method and System for Enhanced Verification Through Structural Target Decomposition

Method and System for Enhanced Verification Through Structural Target Decomposition

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method and system for reduction of XOR/XNOR subexpressions in structural design representations

Reduction of XOR/XNOR subexpressions in structural design representations

Enhanced verification through binary decision diagram-based target decomposition

Method and system for reduction of AND/OR subexpressions in structural design representations

Method and system for reduction of and/or subexpressions in structural design representations

Method and system for performing heuristic constraint simplification

Method and system for performing heuristic constraint simplification

System for verification using reachability overapproximation

Computer program product for verification using reachability overapproximation

Enhanced verification through binary decision diagram-based target decomposition using state analysis extraction

Trace equivalence identification through structural isomorphism detection with on the fly logic writing

Enhanced structural redundancy detection

Method and system for verifying the equivalence of digital circuits

Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver

Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Method and system for predicate selection in bit-level compositional transformations

Extending incremental verification of circuit design to encompass verification restraints

Method for predicate-based compositional minimization in a verification environment

Using constraints in design verification

Method and system for performing heuristic constraint simplification

Method and system for performing minimization of input count during structural netlist overapproximation

Method and system for performing target enlargement in the presence of constraints

Method and system for enhanced verification through binary decision diagram-based target decomposition

Method and system for enhanced verification through structural target decomposition

Method and system for parametric reduction of sequential designs

Method for preserving constraints during sequential reparameterization

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method for heuristic preservation of critical inputs during sequential reparameterization

Method and system for reversing the effects of sequential reparameterization on traces

Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms

System and method for engine-controlled case splitting within multiple-engine based verification framework

Method and system for reduction of and/or subexpressions in structural design representations

Method and system for reduction of XOR/XNOR subexpressions in structural design representations

Method for retiming in the presence of verification constraints

Exploiting suspected redundancy for enhanced design verification

Design verification using sequential and combinational transformations

Method for verification using reachability overapproximation

Method for incremental design reduction via iterative overapproximation and re-encoding strategies

Use of time step information in a design verification system