Steven M. SHANK

BIPOLAR TRANSISTORS

SEMICONDUCTOR RING SURROUNDING VERTICAL DIODE AND RELATED METHODS

BIPOLAR TRANSISTOR STRUCTURES WITH SEMICONDUCTOR BASE FILM WITHIN ISOLATION LAYER, AND RELATED METHODS

HETEROJUNCTION BIPOLAR TRANSISTORS

ISOLATION STACK FOR A BIPOLAR TRANSISTOR AND RELATED METHODS

STRUCTURE WITH PORTIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS AND RELATED METHODS

HETEROJUNCTION BIPOLAR TRANSISTOR

STRUCTURE AND RELATED METHOD FOR SOURCE/DRAIN TERMINAL WITHIN SUBCOLLECTOR

CHIP INCLUDING SILICON DEVICE AND III-V SEMICONDUCTOR DEVICE ON III-V SEMICONDUCTOR LAYER

BIPOLAR TRANSISTOR STRUCTURES WITH SEMICONDUCTOR FILM AND RELATED METHODS

HETEROJUNCTION BIPOLAR TRANSISTOR

BIPOLAR TRANSISTOR STRUCTURES WITH SLOPED BASE SIDEWALLS AND RELATED METHODS

Isolation stack for a bipolar transistor and related methods

HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION

Bipolar transistor

HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION

SILICON CONTROLLED RECTIFIERS

TRANSISTOR STRUCTURES WITH INTERLEAVED BODY CONTACTS AND GATE CONTACTS

IC STRUCTURE WITH GATE ELECTRODE FULLY WITHIN V-SHAPED CAVITY

STRUCTURES WITH BURIED FLUIDIC CHANNELS

Structure with substrate-embedded arrow waveguide and method

SEMICONDUCTOR DEVICE STRUCTURES ISOLATED BY POROUS SEMICONDUCTOR MATERIAL

Electro-absorption modulators with stacked waveguide tapers

Structure including grating coupler with optofluidic grating channels

WAVEGUIDE STRUCTURES

Heterojunction bipolar transistor with buried trap rich isolation region

FIELD EFFECT TRANSISTOR WITH SHALLOW TRENCH ISOLATION FEATURES WITHIN SOURCE/DRAIN REGIONS

Photodiodes

Field-effect transistors having a gate electrode positioned inside a substrate recess

Heterojunction bipolar transistor with buried trap rich isolation region

Photonics structures having a locally-thickened dielectric layer

Spot-size converters with angled facets

Edge couplers integrated with dual ring resonators

STRUCTURE PROVIDING POLY-RESISTOR UNDER SHALLOW TRENCH ISOLATION AND ABOVE HIGH RESISTIVITY POLYSILICON LAYER

IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation

Structure including resistor network for back biasing FET stack

Field-effect transistors with a crystalline body embedded in a trench isolation region

Contact-over-active-gate transistor structures with contacts landed on enlarged gate portions

IC structure including porous semiconductor layer under trench isolations adjacent source/drain regions

IC structure including porous semiconductor layer under trench isolation

Transistor with air gap under raised source/drain region in bulk semiconductor substrate

Efuse inside and gate structure on triple-well region

Bulk substrates with a self-aligned buried polycrystalline layer

Gate contacts with airgap isolation

Photodetector with buried airgap reflectors

Field effect transistor with shallow trench isolation features within source/drain regions

Field effect transistor

Switchable polarization rotators

Photodiode with integrated, self-aligned light focusing element

Device including optofluidic sensor with integrated photodiode

Polysilicon resistor with continuous u-shaped polysilicon resistor elements and related method

Transistor with embedded isolation layer in bulk substrate

Local interconnect layer with device within second dielectric material, and related methods

Structure providing poly-resistor under shallow trench isolation and above high resistivity polysilicon layer

FIELD EFFECT TRANSISTOR (FET) STACK AND METHODS TO FORM SAME

Optical components in the back-end-of-line stack of a photonics chip using plural cores vertically stacked

Bulk wafer switch isolation

Metal-free fuse structures

Transistor with air gap under source/drain region in bulk semiconductor substrate

Thermally and electrically conductive interconnects

Semiconductor structure with in-device high resistivity polycrystalline semiconductor element and method

Pixel arrays including heterogenous photodiode types

Heterojunction bipolar transistor with buried trap rich isolation region

Heterojunction bipolar transistor with buried trap rich isolation region

Photodiode with integrated, light focusing element

Bulk wafer switch isolation

Structure including polycrystalline resistor with dopant-including polycrystalline region thereunder

Semiconductor structures with body contact regions embedded in polycrystalline semiconductor material

DEVICE COMPRISING AN OPTOFLUIDIC SENSOR WITH INTEGRATED PHOTODIODE

Isolation trenches augmented with a trap-rich layer

Vertically stacked field effect transistors

Transistor with embedded isolation layer in bulk substrate

Waveguide structures

Field-effect transistors with a polycrystalline body in a shallow trench isolation region

Field effect transistor (FET) stack and methods to form same

Avalanche photodiode

Photodetector with buried airgap reflectors

Trap-rich layer in a high-resistivity semiconductor layer

Polarization switches including a phase change material

Heterojunction bipolar transistors with one or more sealed airgap

Wafer with crystalline silicon and trap rich polysilicon layer

Field effect transistors with back gate contact and buried high resistivity layer

Transistors with lattice structure

Trench-based photodiodes

Vertical field effect transistor (FET) with source and drain structures

Photodetectors with a lateral composition gradient

Multi-depth regions of high resistivity in a semiconductor substrate

Heterojunction bipolar transistor with emitter base junction oxide interface

Complementary transistor structures formed with the assistance of doped-glass layers

Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material

Vertically stacked field effect transistors

Bulk substrates with a self-aligned buried polycrystalline layer

Semiconductor structures including stacked depleted and high resistivity regions

Photodiodes integrated into a BiCMOS process

Waveguide structures

Field-effect transistors with vertically-serpentine gates

Field-effect transistors with laterally-serpentine gates

Heterojunction bipolar transistor with emitter base junction oxide interface

Bragg gratings with airgap cladding

Heterogeneous directional couplers for photonics chips