Inventor profile of:

Chii-Ping Chen

City:

Hsinchu

Country:

Taiwan

Published Applications:

32

Last publication date:

2025-11-27

Top Assignees for applications by Chii-Ping Chen

The entities that hold a legal rights for patent applications filed by inventor Chen Chii-Ping:

Recent patent applications by Chen Chii-Ping

Chii-Ping Chen from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-11-27
US20250364328A1
Electricity

SELF-ALIGNED SCHEME FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

#2 | 2025-11-06
US20250343095A1
Electricity

THERMAL DISSIPATION IN SEMICONDUCTOR DEVICES

#3 | 2024-06-13
US20240194559A1
Electricity

THERMAL DISSIPATION IN SEMICONDUCTOR DEVICES

#4 | 2024-01-18
US20240021494A1
Electricity

SEMICONDUCTOR DEVICES AND METHOD FOR FORMING THE SAME

#5 | 2023-12-21
US20230411210A1
Electricity

SELF-ALIGNED SCHEME FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

#6 | 2023-11-23
US20230377966A1
Electricity

SELF-ALIGNED SCHEME FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

#7 | 2023-11-16
US20230369226A1
Electricity

SEMICONDUCTOR DEVICE STRUCTURE WITH BARRIER LAYER AND METHOD FOR FORMING THE SAME

#8 | 2023-10-19
US20230335499A1
Electricity

DIFFUSION BARRIER LAYER FOR CONDUCTIVE VIA TO DECREASE CONTACT RESISTANCE

#9 | 2023-10-12
US20230326795A1
Electricity

Semiconductor device structure with resistive element

#10 | 2023-09-14
US20230290678A1
Electricity

BARRIER FREE INTERFACE BETWEEN BEOL INTERCONNECTS

#11 | 2023-08-24
US20230268176A1
Electricity

Method for manufacturing semiconductor structure with resistive elements

#12 | 2022-11-10
US20220359266A1
Electricity

INTER-WIRE CAVITY FOR LOW CAPACITANCE

#13 | 2022-10-06
US20220319987A1
Electricity

Semiconductor device structure with resistive element

#14 | 2022-10-06
US20220319922A1
Electricity

Self-aligned scheme for semiconductor device and method of forming the same

#15 | 2022-09-29
US20220310526A1
Electricity

Diffusion barrier layer for conductive via to decrease contact resistance

#16 | 2022-09-29
US20220310472A1
Electricity

Thermal dissipation in semiconductor devices

#17 | 2022-09-01
US20220277991A1
Electricity

Self-aligned scheme for semiconductor device and method of forming the same

#18 | 2022-04-28
US20220130727A1
Electricity

Semiconductor device structure with resistive element

#19 | 2022-01-27
US20220028752A1
Electricity

Semiconductor devices and method for forming the same

#20 | 2021-10-28
US20210335690A1
Electricity

Thermal dissipation in semiconductor devices

#21 | 2021-10-28
US20210335663A1
Electricity

Barrier free interface between beol interconnects

#22 | 2021-10-28
US20210335655A1
Electricity

Inter-wire cavity for low capacitance

#23 | 2021-09-16
US20210287994A1
Electricity

Diffusion barrier layer for conductive via to decrease contact resistance

#24 | 2021-08-12
US20210249251A1
Electricity

Semiconductor device structure with resistive elements

#25 | 2021-04-01
US20210098290A1
Electricity

Self-aligned scheme for semiconductor device and method of forming the same

#26 | 2020-04-16
US20200118876A1
Electricity

Method for forming semiconductor device with resistive element

#27 | 2019-09-12
US20190279933A1
Electricity

Semiconductor device structure with resistive element

#28 | 2019-05-09
US20190139826A1
Electricity

Structure and formation method of semiconductor device with resistive element

#29 | 2019-05-09
US20190139754A1
Electricity

Structure and formation method of semiconductor device with resistive elements

#30 | 2018-11-22
US20180337125A1
Electricity

Semiconductor device structure with resistive element

#31 | 2018-05-31
US20180151665A1
Electricity

Semiconductor device and layout method

#32 | 2014-09-04
US20140248768A1
Electricity

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InventorID:

5228847 ⎘