Hsinchu
Taiwan
42
2025-11-27
The entities that hold a legal rights for patent applications filed by inventor SHEN Tzer-Min:
Tzer-Min SHEN from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
DIPOLES IN SEMICONDUCTOR DEVICES
#2 | 2025-11-27SEMICONDUCTOR DEVICE WITH TUNABLE THRESHOLD VOLTAGE AND METHOD FOR MANUFACTURING THE SAME
#3 | 2025-11-13GATE STRUCTURE IN SEMICONDUCTOR METHOD AND METHOD OF FORMING THE SAME
#4 | 2025-02-20GATE STRUCTURE IN SEMICONDUCTOR METHOD AND METHOD OF FORMING THE SAME
#5 | 2024-11-28GRAPHENE LAYER FOR LOW RESISTANCE CONTACTS AND DAMASCENE INTERCONNECTS
#6 | 2024-11-14SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
#7 | 2024-09-19EFFECTIVE WORK FUNCTION TUNING VIA SILICIDE INDUCED INTERFACE DIPOLE MODULATION FOR METAL GATES
#8 | 2024-07-11MEMORY CIRCUIT AND WRITE METHOD
#9 | 2024-05-30DIPOLES IN SEMICONDUCTOR DEVICES
#10 | 2024-02-22Semiconductor device structure with channel and method for forming the same
#11 | 2024-01-18SEMICONDUCTOR DEVICE WITH TUNABLE THRESHOLD VOLTAGE AND METHOD FOR MANUFACTURING THE SAME
#12 | 2023-12-21Integrated circuit structure and method with hybrid orientation for FinFET
#13 | 2023-11-16Semiconductor devices including FTJ structure
#14 | 2023-11-092D-channel transistor structure with source-drain engineering
#15 | 2023-05-11Spacer structure for semiconductor device and method for forming the same
#16 | 2023-04-06Effective work function tuning via silicide induced interface dipole modulation for metal gates
#17 | 2023-03-16Memory circuit and write method
#18 | 2023-01-12Gate structure in semiconductor device and method of forming the same
#19 | 2022-12-01Contact structures in semiconductor devices
#20 | 2022-11-10Dual channel structure
#21 | 2022-10-06Semiconductor device structure with channel and method for forming the same
#22 | 2022-09-29Dipoles in semiconductor devices
#23 | 2022-09-08Graphene layer for low resistance contacts and damascene interconnects
#24 | 2022-07-14Effective work function tuning via silicide induced interface dipole modulation for metal gates
#25 | 2022-06-02Semiconductor device and manufacturing method thereof
#26 | 2022-02-10Contact structures in semiconductor devices
#27 | 2022-02-102d-channel transistor structure with source-drain engineering
#28 | 2022-02-03Contact structures in semiconductor devices
#29 | 2022-01-20Spacer structure for semiconductor device and method for forming the same
#30 | 2021-12-02Memory circuit and write method
#31 | 2021-09-30Dual channel structure
#32 | 2021-09-23Integrated circuit structure and method with hybrid orientation for FinFET
#33 | 2020-05-14Integrated circuit structure and method with hybrid orientation for FinFET
#34 | 2019-08-08Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage
#35 | 2019-08-01Negative capacitance finFET and method of fabricating thereof
#36 | 2019-01-03Integrated circuit structure and method with hybrid orientation for FinFET
#37 | 2016-12-15Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage
#38 | 2015-07-09MOSFET structure with T-shaped epitaxial silicon channel
#39 | 2015-06-11Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage
#40 | 2013-10-24SOI transistors with improved source/drain structures with enhanced strain
#41 | 2013-05-09MOSFET structure with T-shaped epitaxial silicon channel
#42 | 2013-05-09Method for forming a semiconductor transistor device with optimized dopant profile
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