John Dinh

Nonvolatile memory devices, systems and methods with switching charge pump architectures

Memory device with adaptive noise and voltage suppression during read-while-write operations

Write parameter switching in a memory device

Ultra-deep power down mode control in a memory device

Memory device ultra-deep power-down mode exit control

Circuits and systems having low power power-on-reset and/or brown out detection

Resistive switching memory having a resistor, diode, and switch memory cell

Memory cells with vertically integrated tunnel access device and programmable impedance element

Capacitor arrangements using a resistive switching memory cell structure

Common plate switching reduction in resistive switching memory devices

Resistive memory device with ramp-up/ramp-down program/erase pulse

Programmable impedance element circuits and methods

Programmable window of operation for CBRAM

Safeguarding data through an SMT process

Current source circuits and methods for mass write and testing of programmable impedance elements

Memory devices, architectures and methods for memory elements having dynamic change in property

Sensing data in resistive switching memory devices

Read methods, circuits and systems for memory devices

Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse

Programmable impedance element circuits and methods

Variable impedance memory device having simultaneous program and erase, and corresponding methods and circuits