Susan E. Eisen

Fast mapper restore for flush in processor

Routing instruction results to a register block of a subdivided register file based on register block utilization rate

Prioritization of threads in a simultaneous multithreading processor core

Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry

Instruction dispatch routing

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

Redistribution of architected states for a processor register file

Check pointing of accumulator register results in a microprocessor

Logical register recovery within a processor

System and handling of register data in processors

System and handling of register data in processors

Saving and restoring a transaction memory state

Supporting speculative microprocessor instruction execution

Completion mechanism for a microprocessor instruction completion table

Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor

Logical register recovery within a processor

Flush-recovery bandwidth in a processor

Instruction completion table with ready-to-complete vector

Mechanism to stop completions using stop codes in an instruction completion table

Mechanism for completing atomic instructions in a microprocessor

Completion mechanism for a microprocessor instruction completion table

Instruction completion table containing entries that share instruction tags

Speculative execution of both paths of a weakly predicted branch instruction

Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor

Thread transition management

Finish status reporting for a simultaneous multithreading processor using an instruction completion table

Prioritized instructions in an instruction completion table of a simultaneous multithreading processor

On-demand multi-tiered hang buster for SMT microprocessor

Speeding up younger store instruction execution after a sync instruction

Thread transition management

Executing system call vectored instructions in a multi-slice processor

Executing system call vectored instructions in a multi-slice processor

FPSCR STICKY BIT HANDLING FOR OUT OF ORDER INSTRUCTION EXECUTION

Thread transition management

Operation of a multi-slice processor with history buffers storing transaction memory state information

Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture

Method and apparatus for managing a speculative transaction in a processing unit

Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions

Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data

Efficiently managing speculative finish tracking and error handling for load instructions

Efficiently managing speculative finish tracking and error handling for load instructions

Thread transition management

Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories

Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

Speeding up younger store instruction execution after a sync instruction

Thread transition management

Completion arbitration for more than two threads based on resource limitations

Tracking effective addresses in an out-of-order processor