Hsinchu
Taiwan
169
2026-06-04
The entities that hold a legal rights for patent applications filed by inventor YEH Der-Chyang:
Der-Chyang YEH from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
SYSTEM-ON-WAFER AND METHODS OF FORMING THE SAME
#2 | 2026-03-26INTEGRATED CIRCUIT PACKAGE AND METHOD
#3 | 2025-11-20PACKAGING OF DIES INCLUDING TSVs USING SACRIFICIAL CARRIER
#4 | 2025-11-13INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME
#5 | 2025-11-13INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME
#6 | 2025-11-13INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME
#7 | 2025-11-06FORMING SHALLOW TRENCH FOR DICING AND STRUCTURES THEREOF
#8 | 2025-10-23INTEGRATED CIRCUIT PACKAGE AND METHOD
#9 | 2025-10-23SEAL RINGS IN INTEGRATED CIRCUIT PACKAGE AND METHOD
#10 | 2025-10-23STRESS BUFFER IN INTEGRATED CIRCUIT PACKAGE AND METHOD
#11 | 2025-10-23SEMICONDUCTOR PACKAGE AND METHOD
#12 | 2025-10-02Semiconductor Device and Method
#13 | 2025-09-25PACKAGES WITH METAL LINE CRACK PREVENTION DESIGN
#14 | 2025-08-28DEVICES EMPLOYING THERMAL AND MECHANICAL ENHANCED LAYERS AND METHODS OF FORMING SAME
#15 | 2025-08-21INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME
#16 | 2025-05-22INTEGRATED CIRCUIT PACKAGE AND METHOD
#17 | 2025-05-01SEMICONDUCTOR PACKAGE AND METHOD
#18 | 2024-12-19DEVICE PACKAGE WITH HETEROGENEOUS DIE STRUCTURES AND METHODS OF FORMING SAME
#19 | 2024-12-19DIE STITCHING FOR STACKING ARCHITECTURE IN SEMICONDUCTOR PACKAGES
#20 | 2024-12-12FORMING SHALLOW TRENCH FOR DICING AND STRUCTURES THEREOF
#21 | 2024-12-12SEAL RINGS IN INTEGRATED CIRCUIT PACKAGE AND METHOD
#22 | 2024-12-12STRESS BUFFER IN INTEGRATED CIRCUIT PACKAGE AND METHOD
#23 | 2024-11-21Via for Component Electrode Connection
#24 | 2024-10-10Packaging of Dies Including TSVs using Sacrificial Carrier
#25 | 2024-08-22Structure and Method of Forming a Joint Assembly
#26 | 2024-07-25VIA FOR SEMICONDUCTOR DEVICE CONNECTION
#27 | 2024-05-16SEMICONDUCTOR DEVICE AND METHOD
#28 | 2024-03-14PACKAGES WITH METAL LINE CRACK PREVENTION DESIGN
#29 | 2024-03-07Redistribution Layer Structures for Integrated Circuit Package
#30 | 2024-02-15INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME
#31 | 2024-02-08Integrated Circuit Package and Method of Forming the Same
#32 | 2023-12-14Methods of Forming Packages and Resulting Structures
#33 | 2023-11-30Stacked semiconductor devices and methods of forming same
#34 | 2023-11-23Integrated Circuit Packages and Methods of Forming the Same
#35 | 2023-10-19Integrated Circuit Packages and Methods of Forming the Same
#36 | 2023-10-19SEMICONDUCTOR PACKAGES
#37 | 2023-08-03Wafer level chip scale packaging intermediate structure apparatus and method
#38 | 2023-08-03Fan-out structure and method of fabricating the same
#39 | 2023-06-29Semiconductor package for thermal dissipation
#40 | 2022-11-24Stacked semiconductor devices and methods of forming same
#41 | 2022-11-17Redistribution structure for integrated circuit package and method of forming same
#42 | 2022-11-10Opening in the pad for bonding integrated passive device in InFO package
#43 | 2022-11-10Devices Employing Thermal and Mechanical Enhanced Layers and Methods of Forming Same
#44 | 2022-11-10Via for semiconductor device connection and methods of forming the same
#45 | 2022-11-10Via for component electrode connection
#46 | 2022-11-03Pad structure design in fan-out package
#47 | 2022-09-22Structure and method of forming a joint assembly
#48 | 2022-09-08Integrated circuit package pad and methods of forming
#49 | 2022-05-26Raised via for terminal connections on different planes
#50 | 2022-03-03Semiconductor structure
#51 | 2021-12-02Packages and methods of forming packages
#52 | 2021-11-18Redistribution structure for integrated circuit package and method of forming same
#53 | 2021-11-11Redistribution layer structures for integrated circuit package
#54 | 2021-11-04Semiconductor package and method
#55 | 2021-10-21Packages with metal line crack prevention design
#56 | 2021-09-30Wafer level chip scale packaging intermediate structure apparatus and method
#57 | 2021-09-09Semiconductor Device and Method
#58 | 2021-07-15Chip on Package Structure and Method
#59 | 2021-06-24Redistribution layers in semiconductor packages and methods of forming same
#60 | 2021-06-24Fan-out structure and method of fabricating the same
#61 | 2021-06-17Opening in the pad for bonding integrated passive device in InFO package
#62 | 2021-04-08Stacked semiconductor devices and methods of forming same
#63 | 2021-02-25Semiconductor package for thermal dissipation
#64 | 2021-02-04Devices employing thermal and mechanical enhanced layers and methods of forming same
#65 | 2021-02-04Integrated circuit package pad and methods of forming
#66 | 2021-01-21Package with bridge die for interconnection and method forming same
#67 | 2021-01-07Multi-stacked package-on-package structures
#68 | 2020-11-26Semiconductor package and method of forming the same
#69 | 2020-10-29Semiconductor package and method of forming the same
#70 | 2020-10-15Package with passive devices and method of forming the same
#71 | 2020-09-17Package structures and methods of forming
#72 | 2020-09-17Wafer level chip scale packaging intermediate structure apparatus and method
#73 | 2020-09-10Redistribution layer structures for integrated circuit package
#74 | 2020-09-10Multi-chip structure and method of forming same
#75 | 2020-08-13Fan-out structure and method of fabricating the same
#76 | 2020-08-06Raised via for terminal connections on different planes
#77 | 2020-07-30Via for semiconductor device connection and methods of forming the same
#78 | 2020-06-04Redistribution layers in semiconductor packages and methods of forming same
#79 | 2020-04-16Packages and methods of forming packages
#80 | 2020-04-16Semiconductor structure
#81 | 2020-03-19Alignment mark design for packages
#82 | 2020-03-19Pad structure design in fan-out package
#83 | 2020-03-12Semiconductor package and method of forming the same
#84 | 2020-03-12Dummy metal with zigzagged edges
#85 | 2020-03-12Interconnect structure for package-on-package devices
#86 | 2020-03-12Integrated circuit package pad and methods of forming
#87 | 2020-03-05Surface mount device/integrated passive device on package or device structure and methods of forming
#88 | 2020-02-27Multi-stacked package-on-package structures
#89 | 2020-02-27Stacked semiconductor devices and methods of forming same
#90 | 2020-02-20Redistribution layers in semiconductor packages and methods of forming same
#91 | 2020-01-30Semiconductor package and method
#92 | 2020-01-09Semiconductor device and method
#93 | 2020-01-02Structure and method of forming a joint assembly
#94 | 2020-01-02Electric magnetic shielding structure in packages
#95 | 2020-01-02Underfill control structures and method
#96 | 2019-11-28Package with passive devices and method of forming the same
#97 | 2019-11-21Package structure and fabricating method thereof
#98 | 2019-11-14Redistribution layer structures for integrated circuit package
#99 | 2019-11-07Via for coupling attached component upper electrode to substrate
#100 | 2019-10-24Devices employing thermal and mechanical enhanced layers and methods of forming same
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