Hsin-Yu Chen

Burst read with flexible burst length for on-chip memory

Power-up header circuitry for multi-bank memory

Bitline Precharge Techniques

System cache peak power management

Level shift latch circuitry

Circuit with impedance elements connected to sources and drains of pMOSFET headers

Level shifter with bypass

Double pumped memory techniques

Memory device and method of controlling leakage current within such a memory device

Controlling a voltage level of an access signal to reduce access disturbs in semiconductor memories

Memory circuitry with write boost and write assist

Improving read stability of a semiconductor memory

Wordline voltage control within a memory