Kishore Kumar Muchherla

RESEQUENCING DATA PROGRAMMED TO MULTIPLE LEVEL MEMORY CELLS AT A MEMORY SUB-SYSTEM

MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST AND LATENT READ DISTURB

PROGRAM REFRESH WITH GATE-INDUCED DRAIN LEAKAGE

MITIGATING SLOW READ DISTURB IN A MEMORY SUB-SYSTEM

MEMORIES CONFIGUED TO DETERMINE DATA STATES IN RESPONSE TO CHARGES STORED TO CHANNEL MATERIAL STRUCTURES

GENERATING SEMI-SOFT BIT DATA DURING CORRECTIVE READ OPERATIONS IN MEMORY DEVICES

MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM

SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE

VALIDATING READ LEVEL VOLTAGE IN MEMORY DEVICES

MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES

CONDITIONAL VALLEY TRACKING DURING CORRECTIVE READS

ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY TO IMPROVE QUALITY OF SERVICE AND ENERGY REQUIREMENTS IN A MEMORY SUB-SYSTEM

ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY AS A HOST DATA BUFFER IN A MEMORY SUB-SYSTEM

ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY AS A PROGRAM BUFFER IN A MEMORY SUB-SYSTEM

ULTRA-HIGH ENDURANCE STORAGE CLASS MEMORY TO REDUCE STORAGE CAPACITANCE IN A MEMORY SUB-SYSTEM

BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES

DATA RECOVERY IN MEMORY DEVICES

PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMORY DEVICE

CALIBRATING DATA RELOCATION FROM BUFFER TO MEMORY DEVICE IN A MEMORY SUB-SYSTEM

CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA

MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE

PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEMORY DEVICE

CODE RATE AS FUNCTION OF LOGICAL SATURATION

TECHNIQUES FOR MANAGING A VOLTAGE RECOVERY OPERATION

ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE

Automatic wordline status bypass management

PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS

TOUCHUP FOR MEMORY DEVICE USING EMBEDDED ENCODER/DECODER

WORKLOAD-BASED SCAN OPTIMIZATION

ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC

VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE

MITIGATING SLOW READ DISTURB IN A MEMORY SUB-SYSTEM

VOLATILE DATA STORAGE IN NAND MEMORY

MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST AND LATENT READ DISTURB

MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM

Block family-based error avoidance for memory devices

PROVIDING RECOVERED DATA TO A NEW MEMORY CELL AT A MEMORY SUB-SYSTEM BASED ON AN UNSUCCESSFUL ERROR CORRECTION OPERATION

GENERATING SEMI-SOFT BIT DATA DURING CORRECTIVE READ OPERATIONS IN MEMORY DEVICES

Padding cached data with valid data for memory flush commands

Adjustment of code rate as function of memory endurance state metric

Code rate as function of logical saturation

PROGRAM REFRESH WITH GATE-INDUCED DRAIN LEAKAGE

Conditional valley tracking during corrective reads

Managing error-handling flows in memory devices

Parallelized defect detection across multiple sub-blocks in a memory device

Workload-based scan optimization

SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE

CONCURRENT SCAN OPERATION ON MULTIPLE BLOCKS IN A MEMORY DEVICE

Voltage bin calibration based on a voltage distribution reference voltage

Concurrent programming of retired wordline cells with dummy data

VALIDATING READ LEVEL VOLTAGE IN MEMORY DEVICES

Multi-page parity data storage in a memory device

Voltage calibration scans to reduce memory device overhead

Performing a program operation based on a high voltage pulse to securely erase data

USING A COMMON POOL OF BLOCKS FOR USER DATA AND A SYSTEM DATA STRUCTURE

Overwriting at a memory system

Executing a refresh operation in a memory sub-system

Managing error-handling flows in memory devices

Grouping blocks based on power cycle and power on time

Error avoidance based on voltage distribution parameters of block families

Performing a media management operation based on a sequence identifier for a block

Implementing fault tolerant page stripes on low density memory systems

Voltage based combining of block families for memory devices

Error avoidance based on voltage distribution parameters of block families

Error avoidance based on voltage distribution parameters of blocks

Error avoidance based on voltage distribution parameters