Gregory W. ALEXANDER

Slice-based allocation history buffer

Infinite processor thread balancing

Cache miss thread balancing

Data-less history buffer with banked restore ports in a register mapper

Slice-based allocation history buffer

Suppress unnecessary mapping for scratch register

Simplified processor sparing

Managing backend resources via frontend steering or stalls

Cache miss thread balancing

Comparing load instruction address fields to store instruction address fields in a table to delay issuing dependent load instructions

Infinite processor thread balancing

Managing a free list of resources to decrease control complexity and reduce power consumption

Managing a free list of resources to decrease control complexity and reduce power consumption

Managing a free list of resources to decrease control complexity and reduce power consumption

Register file mapping

Dynamic assignment across dispatch pipes of source ports to be used to obtain indication of physical registers

Structure for reducing power consumption for memory device

Structure for reducing power consumption for memory device

Freelist based global completion table having both thread-specific and global completion table identifiers

Freelist based global completion table having both thread-specific and global completion table identifiers

Dynamic issue masks for processor hang prevention

Dynamic issue masks for processor hang prevention

RUN-TIME INSTRUMENTATION HANDLING IN A SUPERSCALAR PROCESSOR

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION

SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction

Program status word dependency handling in an out of order microprocessor design

Collecting computer processor instrumentation data

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Triggering workaround capabilities based on events active in a processor pipeline

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Dual-issuance of microprocessor instructions using dual dependency matrices

Management of cache replacement status in cache memory

Serializing translation lookaside buffer access around address translation parameter modification

Method and system for handling cache coherency for self-modifying code

Branch target preloading using a multiplexer and hash circuit to reduce incorrect branch predictions

Error detection enhancement in a microprocessor through the use of a second dependency matrix

Link stack misprediction resolution