Toronto
Canada
33
2015-01-22
The entities that hold a legal rights for patent applications filed by inventor Sohm Oliver P.:
Oliver P. Sohm from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
Memory time stamp register external to first and second processors
#2 | 2013-11-28Profiling operating context
#3 | 2011-04-28Embedding event information in the timing stream
#4 | 2008-05-22Method for Optimizing Software Implementations of the JPEG2000 Binary Arithmetic Encoder
#5 | 2007-01-04Method and system of indexing into trace data based on entries in a log buffer
#6 | 2007-01-04Method and system of profiling real-time streaming channels
#7 | 2007-01-04Method and system of identifying overlays used by a program
#8 | 2007-01-04SYSTEMS AND METHODS FOR STALL MONITORING
#9 | 2006-12-14Trading off visibility for volume of data when profiling memory events
#10 | 2006-11-23Real-time monitoring, alignment, and translation of CPU stalls or events
#11 | 2006-11-16Method of translating system events into signals for activity monitoring
#12 | 2006-11-16Stored program writing stall information when a processor stalls waiting for another processor
#13 | 2006-11-16Navigating trace data
#14 | 2006-11-16Method and system of identifying overlays
#15 | 2006-11-16Method and system of profiling applications that use virtual memory
#16 | 2006-11-16Profiling operating context and tracing program on a target processor
#17 | 2006-11-16Determining operating context of an executed instruction
#18 | 2006-11-16Monitoring of memory and external events
#19 | 2006-11-16Systems and methods for secure debugging and profiling of a computer system
#20 | 2006-11-16Re-assigning cache line ways
#21 | 2006-11-16Visualizing contents and states of hierarchical storage systems
#22 | 2006-11-16PROVIDING CACHE STATUS INFORMATION ACROSS MULTIPLE CACHE LEVELS
#23 | 2006-11-16Providing information associated with a cache
#24 | 2006-11-16Prioritizing caches having a common cache level
#25 | 2006-11-16Displaying cache information using mark-up techniques
#26 | 2006-11-16Cross-referencing cache line addresses with corresponding names
#27 | 2006-11-16DETERMINING DIFFERENCES BETWEEN CACHED COPIES OF AN ADDRESS
#28 | 2006-11-16VISUALIZING CONTENTS AND STATES OF HIERARCHICAL STORAGE SYSTEMS ACROSS MULTIPLE CORES
#29 | 2006-11-16Cache inspection with inspection bypass feature
#30 | 2006-11-16Determining the presence of a virtual address in a cache
#31 | 2006-11-16WRITING TO A SPECIFIED CACHE
#32 | 2006-11-16Real-time prioritization of stall or event information
#33 | 2006-11-16Embedding event information in the timing stream
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