Inventor profile of:

Yoav Weinberg

City:

Toronto

Country:

Canada

Published Applications:

30

Last publication date:

2026-01-08

Top Assignees for applications by Yoav Weinberg

The entities that hold a legal rights for patent applications filed by inventor Weinberg Yoav:

Recent patent applications by Weinberg Yoav

Yoav Weinberg from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-08
US20260010487A1
Physics

CACHING HOST MEMORY ADDRESS TRANSLATION DATA IN A MEMORY SUB-SYSTEM

#2 | 2025-11-20
US20250355560A1
Physics

MANAGING WRITE COMMAND EXECUTION DURING A POWER FAILURE IN A MEMORY SUB-SYSTEM

#3 | 2025-08-21
US20250266849A1
Electricity

EARLY STOPPING OF BIT-FLIP LOW DENSITY PARITY CHECK DECODING BASED ON SYNDROME WEIGHT

#4 | 2025-07-17
US20250231835A1
Physics

DATA RECOVERY USING ORDERED DATA REQUESTS

#5 | 2025-04-17
US20250123925A1
Physics

PAGE-BY-PAGE LEVEL SHAPING

#6 | 2025-03-06
US20250077455A1
Physics

DATA BURST SUSPEND MODE USING PAUSE DETECTION

#7 | 2025-01-30
US20250036526A1
Physics

COMMAND AND DATA PATH ERROR PROTECTION

#8 | 2025-01-16
US20250021271A1
Physics

COMMAND TIMER INTERRUPT

#9 | 2025-01-02
US20250004962A1
Physics

DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING

#10 | 2024-11-28
US20240396571A1
Electricity

ERROR PROTECTION FOR MANAGED MEMORY DEVICES

#11 | 2024-11-07
US20240370185A1
Physics

POWER EFFICIENT CODEWORD SCRAMBLING IN A NON-VOLATILE MEMORY DEVICE

#12 | 2024-09-26
US20240319873A1
Physics

MANAGING WRITE COMMAND EXECUTION DURING A POWER FAILURE IN A MEMORY SUB-SYSTEM

#13 | 2024-08-15
US20240274211A1
Physics

Voltage detection for managed memory systems

#14 | 2024-07-11
US20240235578A9
Electricity

ERROR PROTECTION FOR MANAGED MEMORY DEVICES

#15 | 2024-07-11
US20240232014A9
Physics

COMMAND AND DATA PATH ERROR PROTECTION

#16 | 2024-07-11
US20240231685A9
Physics

COMMAND TIMER INTERRUPT

#17 | 2024-05-16
US20240160526A1
Physics

Data recovery using ordered data requests

#18 | 2024-05-02
US20240143515A1
Physics

CACHING HOST MEMORY ADDRESS TRANSLATION DATA IN A MEMORY SUB-SYSTEM

#19 | 2024-04-25
US20240134746A1
Physics

Command and data path error protection

#20 | 2024-04-25
US20240134740A1
Electricity

Error protection for managed memory devices

#21 | 2024-04-25
US20240134567A1
Physics

Command timer interrupt

#22 | 2024-02-27
US18048289
Physics

Data recovery using ordered data requests

#23 | 2024-01-02
US18048286
Physics

Error notification using an external channel

#24 | 2023-12-07
US20230396271A1
Electricity

Early stopping of bit-flip low density parity check decoding based on syndrome weight

#25 | 2023-12-07
US20230396269A1
Electricity

Scaled bit flip thresholds across columns for irregular low density parity check decoding

#26 | 2023-12-07
US20230393765A1
Physics

Power efficient codeword scrambling in a non-volatile memory device

#27 | 2023-09-14
US20230289307A1
Physics

Data burst suspend mode using pause detection

#28 | 2023-09-14
US20230289306A1
Physics

Data burst suspend mode using multi-level signaling

#29 | 2023-06-29
US20230207032A1
Physics

Voltage detection for managed memory systems

#30 | 2022-09-15
US20220294473A1
Electricity

Iterative error correction with adjustable parameters after a threshold number of iterations

InventorID:

5521398 ⎘