Boise, Idaho
United States
41
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor McDaniel Terrence B.:
Terrence B. McDaniel from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:
VOLATILE MEMORY DEVICES
#2 | 2025-12-25HETEROGENOUS INTEGRATION OF SEMICONDUCTOR STRUCTURES
#3 | 2025-10-30PROTRUDED BOND PADS FOR HYBRID BONDING OF SEMICONDUCTOR DEVICES
#4 | 2025-10-30SEMICONDUCTOR DEVICES WITH NANO-VIAS, SUCH AS NANO-THROUGH-SILICON VIAS LANDING ON MIDDLE-OF-LINE OR BACK-END-OF-LINE LAYERS
#5 | 2025-10-16SEMICONDUCTOR DEVICE WITH BACKSIDE INTERFACE MECHANISM AND METHODS FOR MANUFACTURING THE SAME
#6 | 2025-08-28Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
#7 | 2024-11-14CONDUCTIVE PAD ON A THROUGH-SILICON VIA
#8 | 2024-08-29DAMASCENE DIGIT LINES
#9 | 2024-05-09Integrated Assemblies and Methods Forming Integrated Assemblies
#10 | 2024-03-07CONNECTING SEMICONDUCTOR DIES THROUGH TRACES
#11 | 2024-02-29SEMICONDUCTOR DEVICE CIRCUITRY FORMED FROM REMOTE RESERVOIRS
#12 | 2024-02-29SEMICONDUCTOR DEVICE INTERCONNECTS FORMED THROUGH VOLUMETRIC EXPANSION
#13 | 2024-02-29SEMICONDUCTOR DEVICE CIRCUITRY FORMED THROUGH VOLUMETRIC EXPANSION
#14 | 2024-02-22METHODS FOR FUSION BONDING SEMICONDUCTOR DEVICES TO TEMPORARY CARRIER WAFERS WITH CAVITY REGIONS FOR REDUCED BOND STRENGTH, AND SEMICONDUCTOR DEVICE ASSEMBLIES FORMED BY THE SAME
#15 | 2024-02-22SEMICONDUCTOR DEVICE ASSEMBLIES WITH A CAVITY EXPOSING THROUGH-SILICON VIAS FOR CONTROLLER ATTACHMENT
#16 | 2024-02-22SEMICONDUCTOR DEVICE ASSEMBLIES WITH CAVITY-EMBEDDED CUBES AND LOGIC-SUPPORTING INTERPOSERS
#17 | 2024-02-01MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS
#18 | 2024-02-01METHODS OF FORMING THE MICROELECTRONIC DEVICES, AND RELATED MICROELECTONIC DEVICES AND ELECTRONIC SYSTEMS
#19 | 2023-10-26Sense line and cell contact for semiconductor devices
#20 | 2023-01-19Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
#21 | 2023-01-05Methods of forming microelectronic devices
#22 | 2022-11-10Integrated assemblies and methods forming integrated assemblies
#23 | 2022-08-04Methods of forming a microelectronic device, and related microelectronic devices, memory devices, and electronic systems
#24 | 2022-03-22Integrated assemblies and methods forming integrated assemblies
#25 | 2022-02-24Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems
#26 | 2022-02-03Digit line formation for horizontally oriented access devices
#27 | 2022-01-27Array of vertical transistors and method used in forming an array of vertical transistors
#28 | 2013-12-05Semiconductor processing method and semiconductor structure
#29 | 2010-12-02Semiconductor processing methods
#30 | 2009-09-24Semiconductor constructions
#31 | 2008-07-10Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same
#32 | 2008-05-15Methods of forming semiconductor constructions
#33 | 2008-05-08Semiconductor Structures
#34 | 2007-07-19Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device
#35 | 2007-02-22Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same
#36 | 2007-01-11Semiconductor processing methods
#37 | 2006-12-28Ion implanting methods
#38 | 2006-10-12Methods of forming semiconductor constructions
#39 | 2006-08-24Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line
#40 | 2006-02-23Methods of forming conductive lines
#41 | 2005-01-13Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device
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