Chieh Lee

THREE-DIMENSIONAL MEMORY DEVICE WITH BIT LINE TRANSISTOR

MEMORY PRECHARGE

HIGH PERFORMANCE EMBEDDED 1T1C MEMORY CELLS

MEMORY DEVICE AND MANUFACTURING METHOD AND TEST METHOD OF THE SAME

SEMICONDUCTOR DEVICE WITH A VERTICAL CHANNEL, AND METHOD FOR MANUFACTURING THE SAME

DRAM COMPUTATION CIRCUIT AND METHOD

SENSE AMPLIFIER WITH READ CIRCUIT FOR COMPUTE-IN-MEMORY

MEMORY ARRAY CONNECTIONS

MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

MEMORY DEVICE WITH TWISTED BIT LINES AND METHODS OF MANUFACTURING THE SAME

STRUCTURES OF SRAM CELL AND METHODS OF FABRICATING THE SAME

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

READ-ONLY MEMORY METHOD, LAYOUT, AND DEVICE

MEMORY CIRCUITS, MEMORY STRUCTURES, AND METHODS FOR FABRICATING A MEMORY DEVICE

COMPUTE-IN-MEMORY DEVICE AND METHOD

DRAM COMPUTATION CIRCUIT AND METHOD

MEMORY DEVICE WITH REDUCED AREA

Memory device and method for operating the same

MEMORY DEVICE AND MANUFACTURING METHOD AND TEST METHOD OF THE SAME

MEMORY DEVICE AND OPERATING METHOD OF THE SAME

Memory array connections

Memory device with reduced area

NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY

Memory systems with vertical integration

SEMICONDUCTOR DEVICE WITH A VERTICAL CHANNEL, AND METHOD FOR MANUFACTURING THE SAME

Memory systems with vertical integration

DRAM computation circuit and method

Sense amplifier with read circuit for compute-in-memory

COMPUTE-IN-MEMORY SYSTEMS AND METHODS WITH CONFIGURABLE INPUT AND SUMMING UNITS

Compute-in-memory device and method

Memory circuits, memory structures, and methods for fabricating a memory device