Ching-tzu CHEN

STACKED FET P-N DIODE

TWO-TERMINAL MIXED-IONIC-ELECTRONIC-CONDUCTION RANDOM ACCESS MEMORY (MIECRAM) DEVICE

SEED STRUCTURES IN SEMICONDUCTOR DEVICES AND FABRICATION THEREOF

DAMASCENE INTERCONNECTS WITH BILAYER LINER

STACKED FET WITH METALLIC SOURCE/DRAIN CONTACT

DIRECTIONAL CONDUCTOR INTERCONNECT WITH EMBEDDED VIA

HYBRID INTERCONNECT STRUCTURE WITH TOPOLOGICAL CONDUCTOR INTERFACE LAYER

ULTRAFAST TRANSPORT INTERCONNECTS

LOW-VARIABILITY, HIGH-DENSITY DISC CELL WITH HORIZONTALLY ALIGNED ELECTRODES

ELECTROFORMED ENERGY-EFFICIENT PHASE CHANGE MEMORY DEVICE WITH THIN ACTIVE REGION

PHASE-CHANGE MEMORY CELL WITH SIDEWALL OUTER CONTACT

PHASE CHANGE MEMORY WITH PARTIAL SIDEWALL SPACER CONTACT

CARRIER-RESOLVED HALL MEASUREMENT WITH MULTI-HARMONIC MAGNETORESISTANCE ANALYSIS

STRUCTURE TO REGULATE MULTI-FILAMENT FORMATION ON MEMORY STRUCTURE

LOW DRIFT PHASE CHANGE MATERIAL COMPOSITE MATRIX

SPIN-ORBIT TORQUE MEMORY DEVICES

VERTICAL MAGNETIC TUNNEL JUNCTION DEVICE

Proximity heater to lower RRAM forming voltage

MAGNETIC TUNNEL JUNCTION DEVICE

MULTI-LAYER TOPOLOGICAL INTERCONNECT WITH PROXIMAL DOPING LAYER

PHASE CHANGE MEMORY CELL SIDEWALL HEATER

PHASE CHANGE MULTILAYER HETEROSTRUCTURE WITH MULTIPLE HEATERS

SELF-ALIGNED PATTERNED PROJECTION LINER FOR SIDEWALL ELECTRODE PCM

VERTICAL ULTRA-THIN PCM CELL

TOPOLOGICAL SEMI-METAL INTERCONNECTS

LATERAL PHASE CHANGE MEMORY CELL

Phase change memory with multi-level programming

Phase change memory cell with double active volume

MULTI-LEVEL PROGRAMMING OF PHASE CHANGE MEMORY DEVICE

Embedded heater in a phase change memory material

Topological semi-metal interconnects

Optimized hierarchical scratchpads for enhanced artificial intelligence accelerator core utilization

Heusler-alloy and ferrimagnet based magnetic domain-wall devices for artificial neural network applications

Thin film device with protective layer

Two-dimensional array of four-terminal thin film devices with surface-sensitive conductor layer and method of fabricating the same

Fabricating two-dimensional array of four-terminal thin film devices with surface-sensitive conductor layer

Thin film device with protective layer

Thin film device with protective layer

Fabricating two-dimensional array of four-terminal thin film devices with surface-sensitive conductor layer

Thin film device with protective layer

THIN FILM DEPOSITION AND LOGIC DEVICE

THIN FILM DEPOSITION AND LOGIC DEVICE

Side-gate defined tunable nanoconstriction in double-gated graphene multilayers

Side-gate defined tunable nanoconstriction in double-gated graphene multilayers