Poughkeepsie, New York
United States
43
2021-07-29
The entities that hold a legal rights for patent applications filed by inventor Tsai Aaron:
Aaron Tsai from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Reducing cache transfer overhead in a system
#2 | 2021-01-28Translation support for a virtual cache
#3 | 2021-01-28Cache structure using a logical directory
#4 | 2020-08-20Instruction to move data in a right-to-left direction
#5 | 2020-05-14Reducing cache transfer overhead in a system
#6 | 2020-04-02Cache management
#7 | 2019-12-05Cache management
#8 | 2019-07-25Cache miss thread balancing
#9 | 2019-07-11Cache directory that determines current state of a translation in a microprocessor core cache
#10 | 2019-01-17Efficient pointer load and format
#11 | 2019-01-17Efficient pointer load and format
#12 | 2019-01-17Efficient pointer load and format
#13 | 2018-12-20Translation support for a virtual cache
#14 | 2018-12-20Translation support for a virtual cache
#15 | 2018-12-20Cache structure using a logical directory
#16 | 2018-12-20Cache structure using a logical directory
#17 | 2018-12-20Reducing cache transfer overhead in a system
#18 | 2018-12-20Reducing cache transfer overhead in a system
#19 | 2018-12-20Reducing cache transfer overhead in a system
#20 | 2018-09-13Cache miss thread balancing
#21 | 2016-03-31Optimizing grouping of instructions
#22 | 2016-03-31Optimizing grouping of instructions
#23 | 2014-04-17Store data forwarding with no memory model restrictions
#24 | 2014-03-20Target buffer address region tracking
#25 | 2013-12-19Cache set selective power up
#26 | 2013-12-12Target buffer address region tracking
#27 | 2011-12-29High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction
#28 | 2011-12-15Managing cache coherency for self-modifying code in an out-of-order execution system
#29 | 2009-09-24Method, system, and computer program product for cross-invalidation handling in a multi-level private cache
#30 | 2009-08-27Method, system and computer program product for storing external device result data
#31 | 2009-08-27Method and system for a multi-level virtual/real cache system with synonym resolution
#32 | 2009-08-27System, method and processor for accessing data after a translation lookaside buffer miss
#33 | 2009-08-20Store data forwarding with no memory model restrictions
#34 | 2009-08-20Specialized store queue and buffer design for silent store implementation
#35 | 2009-08-20Obtaining data in a pipelined processor
#36 | 2009-08-20Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions
#37 | 2009-08-20Method and system for handling cache coherency for self-modifying code
#38 | 2009-08-20Method and system for implementing store buffer allocation
#39 | 2009-08-13Method, system, and computer program product for handling errors in a cache without processor core recovery
#40 | 2009-08-13System and method for avoiding deadlocks when performing storage updates in a multi-processor environment
#41 | 2006-05-02Parallel cache interleave accesses with address-sliced directories
#42 | 2006-04-25System and method for simultaneous access of the same line in cache storage
#43 | 2006-01-24System and method for simultaneous access of the same doubleword in cache storage
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