Tony Brewer

METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS

IDENTIFYING MEMORY HOTSPOTS

MULTIPLE CHANNEL MEMORY SYSTEM

METHOD OF EXECUTING PROGRAMMABLE ATOMIC UNIT RESOURCES WITHIN A MULTI-PROCESS SYSTEM

SELF-SCHEDULING THREADS IN A PROCESSOR BASED ON A THRESHOLD ASSOCIATED WITH PIPELINE STAGES

DETECTING INFINITE LOOPS IN A PROGRAMMABLE ATOMIC TRANSACTION

COMBINED WRITE ENABLE MASK AND CREDIT RETURN FIELD

MULTIPLE CHANNEL MEMORY SYSTEM

NETWORK CREDIT RETURN MECHANISMS

METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS

OPTIMIZED COMMAND QUEUES WITH LOW LATENCY

SINGLE FIELD FOR ENCODING MULTIPLE ELEMENTS

EDGE INTERFACE PLACEMENTS TO ENABLE CHIPLET ROTATION INTO MULTI-CHIPLET CLUSTER

DETECTING INFINITE LOOPS IN A PROGRAMMABLE ATOMIC TRANSACTION

Network credit return mechanisms

Edge interface placements to enable chiplet rotation into multi-chiplet cluster

SELF-SCHEDULING THREADS IN A PROGRAMMABLE ATOMIC UNIT

METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS

Method of executing programmable atomic unit resources within a multi-process system

COMMUNICATING A PROGRAMMABLE ATOMIC OPERATOR TO A MEMORY CONTROLLER

Programmable atomic operator resource locking

Detecting infinite loops in a programmable atomic transaction

Method of organizing a programmable atomic unit instruction memory

Network credit return mechanisms

MANAGING HAZARDS IN A MEMORY CONTROLLER

Variable pipeline length in a barrel-multithreaded processor

Single field for encoding multiple elements

MANAGING RETURN PARAMETER ALLOCATION

Method for configuring multiple input-output channels

Detecting infinite loops in a programmable atomic transaction

REDUCING LATENCY FOR MEMORY OPERATIONS IN A MEMORY CONTROLLER

Method of notifying a process or programmable atomic operation traps

Packet arbitration for buffered packets in a network device

Memory access bounds checking for a programmable atomic operator

On-demand programmable atomic kernel loading

Multiple protocol header processing

Transparent packet splitting and recombining

Ordered delivery of data packets based on type of path information in each packet

Payload parity protection for a synchronous interface

Managing hazards in a memory controller

Deferred communications over a synchronous interface

Flow control for a multiple flow control unit interface

Mapping high-speed, point-to-point interface channels to packet virtual channels

Combined write enable mask and credit return field

Self-scheduling threads in a programmable atomic unit

Secondary device detection using a synchronous interface

Reduced sized encoding of packet length field

Packet arbitration for buffered packets in a network device

Dynamic power and thermal loading in a chiplet-based system

Programmable atomic operator resource locking

Method of notifying a process or programmable atomic operation traps

STATIC IDENTIFIERS FOR A SYNCHRONOUS INTERFACE

Secondary device detection using a synchronous interface

Initialization sequencing of chiplet I/O channels within a chiplet system

Deferred communications over a synchronous interface

Reducing latency for memory operations in a memory controller

Memory access bounds checking for a programmable atomic operator

Payload parity protection for a synchronous interface

Registering a custom atomic operation with the operating system

Method of completing a programmable atomic transaction by ensuring memory locks are cleared

On-demand programmable atomic kernel loading

Variable pipeline length in a barrel-multithreaded processor

Communicating a programmable atomic operator to a memory controller

IDENTIFYING MEMORY HOTSPOTS

Method of organizing a programmable atomic unit instruction memory

Multiple protocol header processing

Optional path ordering in packet-based network

Combined write enable mask and credit return field

Reduced sized encoding of packet length field

Transparent packet splitting and recombining

Single field for encoding multiple elements

Flow control for a multiple flow control unit interface

Method for configuring multiple input-output channels

Ordered delivery of data packets based on type of path information in each packet

Mapping high-speed, point-to-point interface channels to packet virtual channels

Network credit return mechanisms

Memory controller implemented error correction code memory

Memory controller implemented error correction code memory

Multistate development workflow for generating a custom instruction set reconfigurable processor

Multistage development workflow for generating a custom instruction set reconfigurable processor

Systems and methods for selectively controlling multithreaded execution of executable code segments

Systems and methods for mapping a neighborhood of data to general registers of a processing element

Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor

DYNAMICALLY-SELECTABLE VECTOR REGISTER PARTITIONING

Microprocessor architecture having alternative memory access paths

Dispatch mechanism for dispatching instructions from a host processor to a co-processor

Compiler for generating an executable comprising instructions for a plurality of different instruction sets

Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set