Lucian Codrescu

COMPUTING A FRACTIONAL EXPONENTIONAL WITHIN A SOFTMAX ACTIVATION FUNCTION USING A MATRIX MULTIPLICATION HARDWARE ACCELERATOR

SYSTEM AND METHOD OF PRIORITY-BASED INTERRUPT STEERING

Instruction-based synchronization of operations including at least one SIMD scatter operation

SCATTER TO GATHER OPERATION

TABLE LOOKUP USING SIMD INSTRUCTIONS

Systems and methods of using a hypervisor to assign virtual processor priority based on task priority and to schedule virtual processors for guest operating systems

Coprocessor for out-of-order loads

Methods and apparatus for storage and translation of entropy encoded software embedded within a memory hierarchy

Multiple clustered very long instruction word processing core

PARALLELIZATION OF SCALAR OPERATIONS BY VECTOR PROCESSORS USING DATA-INDEXED ACCUMULATORS IN VECTOR REGISTER FILES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA

Dedicated arithmetic encoding instruction

Increasing canny filter implementation speed

Systems and methods of executing multiple hypervisors using multiple sets of processors

Systems and methods of using a hypervisor with guest operating systems and virtual processors

CYCLE SLICED VECTORS AND SLOT EXECUTION ON A SHARED DATAPATH

Externally programmable memory management unit

PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR

Executing an operating system on processors having different instruction set architectures

Vector register addressing and functions based on a scalar register data value

Configurable cache and method to configure same

Overlap checking for a translation lookaside buffer (TLB)

Data cache way prediction

Register files for a digital signal processor operating in an interleaved multi-threaded environment

Instruction cache having a multi-bit way prediction mask

CONFIGURABLE TRANSLATION LOOKASIDE BUFFER

Cache memory with write through, no allocate mode

System and method to perform feature detection and to determine a feature score

System and method to determine feature candidate pixels of an image

Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors

Bimodal Compare Predictor Encoded In Each Compare Instruction

Accelerated video compression multi-tap filter and bilinear interpolator

Systems and methods for cache line replacement

Floating point constant generation instruction

Using the least significant bits of a called function's address to switch processor modes

Use of Loop and Addressing Mode Instruction Set Semantics to Direct Hardware Prefetching

Utilizing Negative Feedback from Unexpected Miss Addresses in a Hardware Prefetcher

Hybrid write-through/write-back cache policy managers, and related systems and methods

Non-Allocating Memory Access with Physical Address

Selective Access of a Store Buffer Based on Cache State

Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than threshold

FIFO load instruction

Memory coherency acceleration via virtual machine migration

PROCESSOR CONFIGURED TO PERFORM TRANSACTIONAL MEMORY OPERATIONS

Fast minimum and maximum searching instruction

Executing instruction packet with multiple instructions with same destination by performing logical operation on results of instructions and storing the result to the destination

Computer system with processor local coherency for virtualized input/output

BIT Splitting Instruction

Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form

Table call instruction for frequently called functions

Large Ram Cache

Methods and Apparatus for Constant Extension in a Processor

Methods and Apparatus for Constant Extension in a Processor

Methods and apparatus for storage and translation of entropy encoded software embedded within a memory hierarchy

Configurable cache and method to configure same

Bimodal branch predictor encoded in a branch instruction

System and method to evaluate a data value as an instruction

System and method of processing hierarchical very long instruction packets

System and method to access a portion of a level two memory and a level one memory

Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor

Dedicated Arithmetic Decoding Instruction

Partitioned replacement for cache memory

Real time multithreaded scheduler and scheduling method

Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode

Configurable cache and method to configure same

System and method of processing data using scalar/vector instructions

Methods and systems for allocating interrupts in a multithreaded processor

System and method to execute a linear feedback-shift instruction

Loop Control System and Method

System and method to perform fast rotation operations

Multi-mode register file for use in branch prediction

System and method for generating and using predicates within a single instruction packet

Dual function adder for computing a hardware prefetch address and an arithmetic operation value

Systems and methods for cache line replacements

System and method of data forwarding within an execution unit

Processor and method of determining a normalization count

Multithreaded processor with lock indicator

System and method of selectively accessing a register file

System and method of determining an address of an element within a table

Selective preclusion of a bus access request

Configurable translation lookaside buffer

System and method of executing instructions in a multi-stage data processing pipeline

Method and system to combine multiple register units within a microprocessor

Method and system for a digital signal processor debugging during power transitions

Embedded trace macrocell for enhanced digital signal processor debugging operations

Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor

Method and system for trusted/untrusted digital signal processor debugging operations

Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging

Shared interrupt controller for a multi-threaded processor

System and method of processing data using scalar/vector instructions

Method and system to perform shifting and rounding operations within a microprocessor

Method and system to indicate an exception-triggering page within a microprocessor

Encoding hardware end loop information onto an instruction

Method and system to combine corresponding half word units from multiple register units within a microprocessor

Instruction for producing two independent sums of absolute differences

Viterbi pack instruction

Background thread processing in a multithread digital signal processor

Pointer computation method and system for a scalable, programmable circular buffer

Shared interrupt control method and system for a digital signal processor

Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor

Shared translation look-aside buffer and method